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Date: Mon, 27 Apr 2009 19:51:36 +0300
Message-ID: <f43fc5580904270951o24126367q7bb21d7f25e7d108@mail.gmail.com>
Subject: Re: [Qemu-devel] [PATCH] sparc64 support TSB related MMU registers
From: Blue Swirl <blauwirbel@gmail.com>
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To: Igor Kovalenko <igor.v.kovalenko@gmail.com>
Cc: qemu-devel@nongnu.org

On 4/26/09, Igor Kovalenko <igor.v.kovalenko@gmail.com> wrote:
> On Fri, Apr 24, 2009 at 9:42 PM, Blue Swirl <blauwirbel@gmail.com> wrote:
>
> > On 4/24/09, Igor Kovalenko <igor.v.kovalenko@gmail.com> wrote:
>  >> Hi!
>  >>
>  >>  This change allows reading ultrasparc I/D MMU TSB tag target register
>  >>  and TSB pointer register (8k and 64k).
>  >>  Linux kernel uses TSB for memory management, and with this change it
>  >>  now can use early allocation routines.
>  >>
>  >>  I'm testing with linux-2.6.29.1 minimalistic sparc64 uniprocessor
>  >>  build, now kernel is able to start build device tree.
>  >>  Without the change kernel was not able to handle D-MMU miss while
>  >>  creating first device tree node.
>  >>  Currently it stops shortly after building device tree, trying to find
>  >>  out path to console.
>  >
>  > Nice, though I didn't notice any visible improvement in my tests.
>
>
> Here is the missing part in qemu-sparc64-mmu-pagesize.patch
>  This fixes TLB match code to respect page size, otherwise 4M page
>  mappings may be not found.
>  Also this corrects a typo in get_physical_address_code which uses a
>  register from DMMU instead of IMMU.
>
>  Please apply.

Looks OK. Please resubmit with only the commit changelog material and
a Sign-off. I'm still learning git (with qgit), I don't know how to
trim the commit message yet. Or maybe that is not the "git way"?

>  get_physical_address_data/code probably needs some code reuse refactoring.

True.