From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LzbNF-0001pm-5S for qemu-devel@nongnu.org; Thu, 30 Apr 2009 14:52:45 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LzbND-0001p7-IK for qemu-devel@nongnu.org; Thu, 30 Apr 2009 14:52:44 -0400 Received: from [199.232.76.173] (port=45572 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LzbND-0001p3-95 for qemu-devel@nongnu.org; Thu, 30 Apr 2009 14:52:43 -0400 Received: from fg-out-1718.google.com ([72.14.220.158]:14835) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1LzbNC-0003cc-N2 for qemu-devel@nongnu.org; Thu, 30 Apr 2009 14:52:43 -0400 Received: by fg-out-1718.google.com with SMTP id l27so1240013fgb.8 for ; Thu, 30 Apr 2009 11:52:40 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <49F9E647.8030007@redhat.com> References: <1240364008-7065-1-git-send-email-froydnj@codesourcery.com> <200904301710.38740.paul@codesourcery.com> <49F9D329.3030008@redhat.com> <200904301807.36073.paul@codesourcery.com> <49F9E647.8030007@redhat.com> Date: Thu, 30 Apr 2009 21:52:39 +0300 Message-ID: Subject: Re: [Qemu-devel] [PATCH] [RFC] cleanup cpu-exec.c: consolidate handle_cpu_signal From: Blue Swirl Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Avi Kivity Cc: Paul Brook , Nathan Froyd , qemu-devel@nongnu.org On 4/30/09, Avi Kivity wrote: > Paul Brook wrote: > > > > > > I'd really like to see kvm used to implement something like this (to > > > emulate non-x86 on x86). > > > > > > > > > > It's something I've considered a few times. It gets hairy fairly quickly > though. You're probably also going to hit a world of pain if your host > pagesize is larger than your guest pagesize, > > > > Yes. But realistically your host is going to be either x86 or x86 (in a > few corner cases that no one cares about, x86). Are there targets with page > size < 4K? We don't target VAX. ARM has 2k pages IIRC. Sparc64 has 8k pages and then we have the same case for x86 target. > > and for guests with a software managed TLB shadow paging gets much more > interesting. > > > > > > Hmm, inserting a tlb entry would just create x86 page table entries, no? Inserting an entry may evict a previous entry. I don't think it's too difficult though. > > There's very little of the old code left, and it's bitrotten enough that > there's no point trying to keep it on the offchance that it'll be useful. > > > > > > Sure, starting from scratch sounds much better, this is going to be wildly > different. > > -- > Do not meddle in the internals of kernels, for they are subtle and quick to > panic. > > > >