From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1M6pTX-0002KX-V8 for qemu-devel@nongnu.org; Wed, 20 May 2009 13:21:08 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1M6pTT-0002JO-Nj for qemu-devel@nongnu.org; Wed, 20 May 2009 13:21:07 -0400 Received: from [199.232.76.173] (port=44253 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1M6pTT-0002JE-H5 for qemu-devel@nongnu.org; Wed, 20 May 2009 13:21:03 -0400 Received: from mail-bw0-f175.google.com ([209.85.218.175]:43012) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1M6pTT-0002o1-80 for qemu-devel@nongnu.org; Wed, 20 May 2009 13:21:03 -0400 Received: by bwz23 with SMTP id 23so511355bwz.34 for ; Wed, 20 May 2009 10:21:01 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <20090520162130.GA22109@redhat.com> References: <20090520162130.GA22109@redhat.com> Date: Wed, 20 May 2009 20:21:01 +0300 Message-ID: Subject: Re: [Qemu-devel] [PATCH] qemu: msi irq allocation api From: Blue Swirl Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Michael S. Tsirkin" Cc: Carsten Otte , kvm@vger.kernel.org, Rusty Russell , qemu-devel@nongnu.org, virtualization@lists.linux-foundation.org, Christian Borntraeger , avi@redhat.com On 5/20/09, Michael S. Tsirkin wrote: > define api for allocating/setting up msi-x irqs, and for updating them > with msi-x vector information, supply implementation in ioapic. Please > comment on this API: I intend to port my msi-x patch to work on top of > it. > > Signed-off-by: Michael S. Tsirkin Sparc64 also uses packets ("mondos", not implemented yet) for interrupt vector data, there the packet size is 8 * 64 bits. I think we should aim for a more generic API that covers this case also. For example, irq.c could support opaque packet payload of unspecified/predefined size. MSI packet structure should be defined in ioapic.c. The pci_msi_ops structure could be 'const', or do you expect it to change during execution?