From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MKFVi-0004qZ-Ip for qemu-devel@nongnu.org; Fri, 26 Jun 2009 13:46:50 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MKFVe-0004pR-58 for qemu-devel@nongnu.org; Fri, 26 Jun 2009 13:46:50 -0400 Received: from [199.232.76.173] (port=43806 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MKFVd-0004pO-Tk for qemu-devel@nongnu.org; Fri, 26 Jun 2009 13:46:45 -0400 Received: from mail-fx0-f209.google.com ([209.85.220.209]:37557) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MKFVd-00019z-CJ for qemu-devel@nongnu.org; Fri, 26 Jun 2009 13:46:45 -0400 Received: by fxm5 with SMTP id 5so2057151fxm.34 for ; Fri, 26 Jun 2009 10:46:44 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <200906261840.10828.paul@codesourcery.com> References: <200906261849.43746.uli@suse.de> <200906261840.10828.paul@codesourcery.com> Date: Fri, 26 Jun 2009 20:46:44 +0300 Message-ID: Subject: Re: [Qemu-devel] [RFC PATCH] s390x-linux-user From: Blue Swirl Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paul Brook Cc: qemu-devel@nongnu.org On 6/26/09, Paul Brook wrote: > On Friday 26 June 2009, Blue Swirl wrote: > > On 6/26/09, Ulrich Hecht wrote: > > > There is a very peculiar S/390 instruction called "EXECUTE". What it > > > does is to take another instruction stored somewhere in memory, > > > logical-OR the second byte of the instruction with the LSB of R0 and then > > > execute the result, without changing the instruction in memory or the > > > program counter. Any idea how to implement this in QEMU? Currently, I'm > > > interpreting the couple of instructions that GCC uses EXECUTE with, but > > > in the long run that would amount to implementing a second emulator... > > > > Maybe something like this: Make a special TB of the EXECUTE > > instruction and add LSB of R0 to TB flags for these TBs. Then you can > > examine R0, OR and generate code at translation time. The TBs linking > > to EXECUTE TB may need to be special too in order to track for R0. > > > That's not sufficient. The results also depend on the referenced instruction. Then add the second byte of the referenced instruction to TB flags? Or maybe just the result of the OR operation for compactness?