Re: [Qemu-devel] [PATCH 0/3] RFC: TCG ARM optimizations

[Blue Swirl <blauwirbel@gmail.com>]

On 6/29/09, Filip Navara <filip.navara@gmail.com> wrote:
>  Lastly, the code generated for softmmu memory loads/stores could
>  probably be optimized in some cases. It uses hard-coded registers.
>  It's not optimized for multiple stores to adjacent locations (pushing
>  multiple registers to stack) and does all the calculations again and
>  again. This results not only in recomputing numbers we already have
>  (as long as the stack is still on the same guest page), but also in
>  huge TBs. I imagine that doesn't help the processor cache too much.
>  This would probably benefit all targets. In fact I believe the softmmu
>  code could be moved out of the TCG target-specific code and into the
>  main code (with the possibility to override it with optimized
>  version).

Interesting. We could add a new optional TCG instruction op_ld_g2h
(extracted from qemu_ld) that performs the TLB lookup and returns the
host address. When multiple accesses near the same guest address are
detected (how?), the translator can reuse the host address, perform
some math and check if the guest page is still same. If true, ld_raw
can be used, otherwise recalculate the host address.

On the performance side, qemu_ld on Sparc host uses 9 instructions in
the TLB hit case before the access. Maybe this would lower the number
a bit but not too much.