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Date: Sun, 12 Jul 2009 11:09:00 +0300
Message-ID: <f43fc5580907120109wd4d3e71j158a01c8c30423@mail.gmail.com>
Subject: Re: [Qemu-devel] [PATCH] sparc64: trap handling corrections
From: Blue Swirl <blauwirbel@gmail.com>
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To: Igor Kovalenko <igor.v.kovalenko@gmail.com>
Cc: qemu-devel@nongnu.org

On 7/12/09, Igor Kovalenko <igor.v.kovalenko@gmail.com> wrote:
> Good trap handling is required to process interrupts.
>  This patch fixes the following:
>
>  - sparc64 has no wim register
>  - sparc64 has no psret register, use IE bit of pstate
>   extract IE checking code to cpu_interrupts_enabled
>  - alternate globals are not available if cpu has GL feature
>   in this case bit AG of pstate is constant zero
>  - write to pstate must actually write pstate
>   even if cpu has GL feature
>
>  Also timer interrupt is handled using do_interrupt.

A bit too much for one patch. Please also remove the code instead of
commenting out.

PUT_PSR for Sparc64 needs CC_OP = CC_OP_FLAGS; like Sparc32.

>  Timer interrupt would require attention later when timers
>  start to tick (currently timers are not really functional).

I think this comment is not true, IIRC at least tick and stick
counters can be read (and they are used by SILO) and also interrupts
work.