From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MSmhI-0004Sh-T8 for qemu-devel@nongnu.org; Mon, 20 Jul 2009 02:50:04 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MSmhH-0004SV-Du for qemu-devel@nongnu.org; Mon, 20 Jul 2009 02:50:03 -0400 Received: from [199.232.76.173] (port=45873 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MSmhH-0004SS-8b for qemu-devel@nongnu.org; Mon, 20 Jul 2009 02:50:03 -0400 Received: from mx20.gnu.org ([199.232.41.8]:38392) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1MSmhG-0006Ai-N7 for qemu-devel@nongnu.org; Mon, 20 Jul 2009 02:50:02 -0400 Received: from fg-out-1718.google.com ([72.14.220.154]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MSmhD-0003TG-5u for qemu-devel@nongnu.org; Mon, 20 Jul 2009 02:49:59 -0400 Received: by fg-out-1718.google.com with SMTP id l27so747154fgb.8 for ; Sun, 19 Jul 2009 23:49:57 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: References: From: Blue Swirl Date: Mon, 20 Jul 2009 09:49:36 +0300 Message-ID: Subject: Re: [Qemu-devel] [PATCH] sparc64 replace tsptr with helper routine Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Igor Kovalenko Cc: qemu-devel@nongnu.org On Mon, Jul 20, 2009 at 12:19 AM, Igor Kovalenko wrote: > tl and tsptr of members sparc64 cpu state must be changed > simultaneously to keep trap state window in sync with current > trap level. Currently translation of store to tl does not change > tsptr, which leads to corrupt trap state on corresponding > trap level. > > This patch removes tsptr from sparc64 cpu state and replaces > all uses with call to helper routine. I'd rather have the stores to TL fixed instead of introducing a helper. A new function to set both TL and tsptr may help. Which stores to TL do not change tsptr? On CPU reset, TL should be MAXTL for POR and MIN(TL+1, MAXTL) in other cases but your patch would set it to 0.