From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MiWOP-0001h2-D5 for qemu-devel@nongnu.org; Tue, 01 Sep 2009 12:39:37 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MiWOJ-0001ZP-VG for qemu-devel@nongnu.org; Tue, 01 Sep 2009 12:39:36 -0400 Received: from [199.232.76.173] (port=35816 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MiWOJ-0001Z4-Md for qemu-devel@nongnu.org; Tue, 01 Sep 2009 12:39:31 -0400 Received: from mx20.gnu.org ([199.232.41.8]:32808) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1MiWOJ-00060t-8I for qemu-devel@nongnu.org; Tue, 01 Sep 2009 12:39:31 -0400 Received: from mail-ew0-f223.google.com ([209.85.219.223]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MiWOI-0001cX-KC for qemu-devel@nongnu.org; Tue, 01 Sep 2009 12:39:30 -0400 Received: by ewy23 with SMTP id 23so121281ewy.8 for ; Tue, 01 Sep 2009 09:39:29 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <476105.70627.qm@web27005.mail.ukl.yahoo.com> References: <476105.70627.qm@web27005.mail.ukl.yahoo.com> From: Blue Swirl Date: Tue, 1 Sep 2009 19:39:09 +0300 Message-ID: Subject: Re: [Qemu-devel] Emulation of early 486 CPUs (no fpu, no cpuid) Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: bifferos Cc: qemu-devel@nongnu.org On Tue, Sep 1, 2009 at 3:05 PM, bifferos wrote: > Hi, > > I'm trying to emulate a 486SX CPU, so was wondering how to knock out cpui= d and fpu. =C2=A0I've changed the definition of ID_MASK in target-i386/cpu.= h to zero, and this prevents Linux from detecting cpuid capability. =C2=A0B= it of a hack, because the instruction is still there, but never mind. =C2= =A0I've been trying to work out how to disable fpu emulation so Linux falls= back on software emulation. > > Can someone throw me a bone? x86 CPU support is a bit primitive compared to PPC, ARM or Sparc. On those targets there are plenty of CPU types to choose from and if that is not enough, there are ways to modify the cpu features. The CPU type also influences instruction translation: without an FPU, floating point instructions trap on Sparc. There may be an order of magnitude more x86 CPU types than all other targets combined, so we may not want to support all of them but at least the x86 feature selection support and translation should be more flexible.