From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MsLBW-0005ht-F9 for qemu-devel@nongnu.org; Mon, 28 Sep 2009 14:42:54 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MsLBR-0005bV-PK for qemu-devel@nongnu.org; Mon, 28 Sep 2009 14:42:54 -0400 Received: from [199.232.76.173] (port=40331 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MsLBR-0005bI-KZ for qemu-devel@nongnu.org; Mon, 28 Sep 2009 14:42:49 -0400 Received: from mail-bw0-f211.google.com ([209.85.218.211]:35812) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MsLBQ-00023P-LA for qemu-devel@nongnu.org; Mon, 28 Sep 2009 14:42:48 -0400 Received: by bwz7 with SMTP id 7so510555bwz.34 for ; Mon, 28 Sep 2009 11:42:47 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <1254156621-28559-1-git-send-email-weil@mail.berlios.de> References: <4AC0E93A.6010605@mail.berlios.de> <1254156621-28559-1-git-send-email-weil@mail.berlios.de> From: Blue Swirl Date: Mon, 28 Sep 2009 21:42:27 +0300 Message-ID: Subject: Re: [Qemu-devel] [PATCH] tcg, tci: Add TCG and interpreter for bytecode (virtual machine) Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Stefan Weil Cc: QEMU Developers , Stefan Weil On Mon, Sep 28, 2009 at 7:50 PM, Stefan Weil wrote: > This is an initial and highly experimental version of > a new code generator which does not create native code > (so it will not depend on the host running qemu when it > is finished). It creates bytecode which is interpreted. > > The current version can run the bios code, a simple > hello world and the linux-user testcode for the > i386 and x86_64 targets on x86_64 hosts. > > Some additional information is in tcg/bytecode/README > which is part of the patch. > > Please send patches / enhancements based on my latest > version from git://repo.or.cz/qemu/ar7.git. Nice. When the interpreter works, it should be unconditional for targets that are not supported by TCG. > +QEMU can create native code for some hosts (arm, hppa, i386, ppc, ppc64, > +sparc, x86_64). For others, inoffical host support was written (s390). unofficial > +static const int tcg_target_call_oarg_regs[2] =3D { > + =C2=A0 =C2=A0// TODO: ppc64 only uses one register. Why do others use t= wo? To pass a 64 bit return value in two 32 bit registers? > +static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] =3D { > +#if TCG_TARGET_NB_REGS =3D=3D 16 || TCG_TARGET_NB_REGS =3D=3D 32 > + =C2=A0 =C2=A0"r16", Table overflow.