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From: Blue Swirl <blauwirbel@gmail.com>
Date: Sat, 19 Dec 2009 21:25:54 +0000
Message-ID: <f43fc5580912191325h788cf6e8kd3cacbe3779be06f@mail.gmail.com>
Subject: Re: [Qemu-devel] [PATCH 5/7] tcg-sparc: Implement setcond, movcond,
	setcond2, brcond2.
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To: Richard Henderson <rth@twiddle.net>
Cc: qemu-devel@nongnu.org

On Sat, Dec 19, 2009 at 5:47 PM, Richard Henderson <rth@twiddle.net> wrote:
> On 12/19/2009 02:31 AM, Blue Swirl wrote:
>>>
>>> =C2=A0static inline void tcg_out_movi_imm32(TCGContext *s, int ret, uin=
t32_t
>>> arg)
>>> =C2=A0{
>>> - =C2=A0 =C2=A0if (check_fit_tl(arg, 12))
>>> + =C2=A0 =C2=A0if (check_fit_tl(arg, 13))
>>> =C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_out_movi_imm13(s, ret, arg);
>>
>> IIRC sign extension prevents this.
>
> Pardon? =C2=A0check_fit_tl checks a signed value, the OR opcode provides =
one.
> =C2=A0Where's the conflict?

Long time ago I tried the same change, but the generated code was not
correct. But now it seems to work.

>>> - =C2=A0 =C2=A0if (const_arg2&& =C2=A0arg2 =3D=3D 0)
>>> - =C2=A0 =C2=A0 =C2=A0 =C2=A0/* orcc %g0, r, %g0 */
>>> - =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_out_arith(s, TCG_REG_G0, TCG_REG_G0, a=
rg1, ARITH_ORCC);
>>> - =C2=A0 =C2=A0else
>>> - =C2=A0 =C2=A0 =C2=A0 =C2=A0/* subcc r1, r2, %g0 */
>>> - =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_out_arith(s, TCG_REG_G0, arg1, arg2, A=
RITH_SUBCC);
>>> - =C2=A0 =C2=A0tcg_out_branch_i32(s, tcg_cond_to_bcond[cond], label_ind=
ex);
>>> + =C2=A0 =C2=A0tcg_out_cmp(s, arg1, arg2, const_arg2);
>>
>> What's wrong with 'orcc' (produces the synthetic instruction 'tst')?
>
> What result does "orcc" give that isn't produced by "subcc"? =C2=A0Unlike=
 i386
> where "test x,x" is one byte smaller than "cmp $0,x", it seems to me ther=
e's
> no reason to distingish the arg2 =3D=3D constant zero case on sparc.

Maybe it's faster on real CPUs. On my machine I don't see any
difference. I timed the following program:

#include <stdio.h>
#include <stdlib.h>

#define N 100000000

int main(int argc, char **argv)
{
    unsigned int i;

    if (atoi(argv[1])) {
        for (i =3D 0; i < N; i++) {
            asm volatile ("cmp %g1, 0");
        }
    } else {
        for (i =3D 0; i < N; i++) {
            asm volatile ("tst %g1");
        }
    }
    return 0;
}