From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43)
	id 1NSXrv-0002fr-It
	for qemu-devel@nongnu.org; Wed, 06 Jan 2010 10:32:19 -0500
Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43)
	id 1NSXrs-0002b8-3W
	for qemu-devel@nongnu.org; Wed, 06 Jan 2010 10:32:19 -0500
Received: from [199.232.76.173] (port=33087 helo=monty-python.gnu.org)
	by lists.gnu.org with esmtp (Exim 4.43) id 1NSXrr-0002as-LN
	for qemu-devel@nongnu.org; Wed, 06 Jan 2010 10:32:15 -0500
Received: from mail-pw0-f43.google.com ([209.85.160.43]:38359)
	by monty-python.gnu.org with esmtp (Exim 4.60)
	(envelope-from <blauwirbel@gmail.com>) id 1NSXrr-00088C-BU
	for qemu-devel@nongnu.org; Wed, 06 Jan 2010 10:32:15 -0500
Received: by pwj11 with SMTP id 11so12229192pwj.2
	for <qemu-devel@nongnu.org>; Wed, 06 Jan 2010 07:32:14 -0800 (PST)
MIME-Version: 1.0
In-Reply-To: <20100105231912.6526.44123.stgit@skyserv>
References: <20100105231558.6526.44483.stgit@skyserv>
	<20100105231912.6526.44123.stgit@skyserv>
From: Blue Swirl <blauwirbel@gmail.com>
Date: Wed, 6 Jan 2010 15:31:54 +0000
Message-ID: <f43fc5581001060731j19b338e9k83dceced3436bc0a@mail.gmail.com>
Subject: Re: [Qemu-devel] [PATCH 2/9] sparc64: add PSR and PIL to cpu state
	dump
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: quoted-printable
List-Id: qemu-devel.nongnu.org
List-Unsubscribe: <http://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.gnu.org/pipermail/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <http://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: "Igor V. Kovalenko" <igor.v.kovalenko@gmail.com>
Cc: qemu-devel@nongnu.org

On Tue, Jan 5, 2010 at 11:19 PM, Igor V. Kovalenko
<igor.v.kovalenko@gmail.com> wrote:
> From: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
>
> Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
> ---
> =C2=A0target-sparc/helper.c | =C2=A0 =C2=A01 +
> =C2=A01 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/target-sparc/helper.c b/target-sparc/helper.c
> index a06923a..0f0e583 100644
> --- a/target-sparc/helper.c
> +++ b/target-sparc/helper.c
> @@ -1452,6 +1452,7 @@ void cpu_dump_state(CPUState *env, FILE *f,
> =C2=A0#ifdef TARGET_SPARC64
> =C2=A0 =C2=A0 cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: =
%d fprs: %d\n",
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 env->pstate, GET_=
CCR(env), env->asi, env->tl, env->fprs);
> + =C2=A0 =C2=A0cpu_fprintf(f, "psr: 0x%08x pil=3D%x\n", GET_PSR(env), env=
->psrpil);

PSR does not exist on Sparc64, instead we have separate registers,
like VER, CWP and CCR. PIL part is OK.