Re: [Qemu-devel] [PATCH 5/9] sparc64: add macros to deal with softint and timer interrupt

[Blue Swirl <blauwirbel@gmail.com>]

On Tue, Jan 5, 2010 at 11:19 PM, Igor V. Kovalenko
<igor.v.kovalenko@gmail.com> wrote:
> From: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
>
> Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
> ---
>  target-sparc/cpu.h |    6 ++++++
>  1 files changed, 6 insertions(+), 0 deletions(-)
>
> diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
> index 1fe4d0f..0dba241 100644
> --- a/target-sparc/cpu.h
> +++ b/target-sparc/cpu.h
> @@ -394,6 +394,8 @@ typedef struct CPUSPARCState {
>     uint64_t fprs;
>     uint64_t tick_cmpr, stick_cmpr;
>     void *tick, *stick;
> +#define TICK_NPT_MASK        0x8000000000000000ULL
> +#define TICK_SOFTINT_DISABLE 0x8000000000000000ULL

Please move the TICK_NPT and TICK_INT_DIS macros from sun4u.c to here.

>     uint64_t gsr;
>     uint32_t gl; // UA2005
>     /* UA 2005 hyperprivileged registers */
> @@ -402,6 +404,10 @@ typedef struct CPUSPARCState {
>     uint32_t softint;
>  #define SOFTINT_TIMER   1
>  #define SOFTINT_STIMER  (1 << 16)
> +#define SOFTINT_INTRMASK (0xFFFE)
> +#define SOFTINT_TM       (1 << 0)
> +#define SOFTINT_SM       (1 << 16)

Why the duplicate definitions?

> +#define SOFTINT_REG_MASK (SOFTINT_SM|SOFTINT_INTRMASK|SOFTINT_TM)
>  #endif
>     sparc_def_t *def;
>  } CPUSPARCState;
>
>
>
>