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From: Blue Swirl <blauwirbel@gmail.com>
Date: Wed, 6 Jan 2010 15:58:16 +0000
Message-ID: <f43fc5581001060758r10487c78s556936e43d415d1d@mail.gmail.com>
Subject: Re: [Qemu-devel] [PATCH 5/9] sparc64: add macros to deal with softint
	and timer interrupt
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To: "Igor V. Kovalenko" <igor.v.kovalenko@gmail.com>
Cc: qemu-devel@nongnu.org

On Tue, Jan 5, 2010 at 11:19 PM, Igor V. Kovalenko
<igor.v.kovalenko@gmail.com> wrote:
> From: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
>
> Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
> ---
> =C2=A0target-sparc/cpu.h | =C2=A0 =C2=A06 ++++++
> =C2=A01 files changed, 6 insertions(+), 0 deletions(-)
>
> diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
> index 1fe4d0f..0dba241 100644
> --- a/target-sparc/cpu.h
> +++ b/target-sparc/cpu.h
> @@ -394,6 +394,8 @@ typedef struct CPUSPARCState {
> =C2=A0 =C2=A0 uint64_t fprs;
> =C2=A0 =C2=A0 uint64_t tick_cmpr, stick_cmpr;
> =C2=A0 =C2=A0 void *tick, *stick;
> +#define TICK_NPT_MASK =C2=A0 =C2=A0 =C2=A0 =C2=A00x8000000000000000ULL
> +#define TICK_SOFTINT_DISABLE 0x8000000000000000ULL

Please move the TICK_NPT and TICK_INT_DIS macros from sun4u.c to here.

> =C2=A0 =C2=A0 uint64_t gsr;
> =C2=A0 =C2=A0 uint32_t gl; // UA2005
> =C2=A0 =C2=A0 /* UA 2005 hyperprivileged registers */
> @@ -402,6 +404,10 @@ typedef struct CPUSPARCState {
> =C2=A0 =C2=A0 uint32_t softint;
> =C2=A0#define SOFTINT_TIMER =C2=A0 1
> =C2=A0#define SOFTINT_STIMER =C2=A0(1 << 16)
> +#define SOFTINT_INTRMASK (0xFFFE)
> +#define SOFTINT_TM =C2=A0 =C2=A0 =C2=A0 (1 << 0)
> +#define SOFTINT_SM =C2=A0 =C2=A0 =C2=A0 (1 << 16)

Why the duplicate definitions?

> +#define SOFTINT_REG_MASK (SOFTINT_SM|SOFTINT_INTRMASK|SOFTINT_TM)
> =C2=A0#endif
> =C2=A0 =C2=A0 sparc_def_t *def;
> =C2=A0} CPUSPARCState;
>
>
>
>