From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NTJOG-0005Uc-9C for qemu-devel@nongnu.org; Fri, 08 Jan 2010 13:16:52 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1NTJOA-0005Mk-Vf for qemu-devel@nongnu.org; Fri, 08 Jan 2010 13:16:51 -0500 Received: from [199.232.76.173] (port=37534 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NTJOA-0005Md-NE for qemu-devel@nongnu.org; Fri, 08 Jan 2010 13:16:46 -0500 Received: from mail-pw0-f43.google.com ([209.85.160.43]:64988) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NTJOA-0007Rk-Am for qemu-devel@nongnu.org; Fri, 08 Jan 2010 13:16:46 -0500 Received: by pwj11 with SMTP id 11so196089pwj.2 for ; Fri, 08 Jan 2010 10:16:45 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <20100107201810.16653.85771.stgit@skyserv> References: <20100107201810.16653.85771.stgit@skyserv> From: Blue Swirl Date: Fri, 8 Jan 2010 18:16:25 +0000 Message-ID: Subject: Re: [Qemu-devel] [PATCH 0/9] sparc64: interrupts and tick timers v1 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Igor V. Kovalenko" Cc: qemu-devel@nongnu.org Thanks, applied all except 9/9. On Thu, Jan 7, 2010 at 8:27 PM, Igor V. Kovalenko wrote: > The following series is a cleanup over previous one. > > v0 -> v1: post-review changes > - dropped patch "clear exception_index with -1 val" (applied) > - new patch "change_pstate should have 32bit argument" > - cleanups for coding style and hexadecimal output convention > - wrpil is no-op for CONFIG_USER_ONLY > - restored PIL 15 as non-maskable interrupt level on sparcv8 > - check for PSTATE.IE is replaced with call to cpu_interrupts_enabled() > - in patch "sparc64: interrupt trap handling" > =C2=A0cleaned up change in cpu_exec; since sparc64 does not use > =C2=A0CPU_INTERRUPT_TIMER now, corresponding code branch is unchanged > > --- > > Igor V. Kovalenko (9): > =C2=A0 =C2=A0 =C2=A0sparc64: change_pstate should have 32bit argument > =C2=A0 =C2=A0 =C2=A0sparc64: trace pstate and global register set changes > =C2=A0 =C2=A0 =C2=A0sparc64: add PIL to cpu state dump > =C2=A0 =C2=A0 =C2=A0sparc64: use helper_wrpil to check pending irq on wri= te > =C2=A0 =C2=A0 =C2=A0sparc64: check for pending irq when pil, pstate or so= ftint is changed > =C2=A0 =C2=A0 =C2=A0sparc64: add macros to deal with softint and timer in= terrupt > =C2=A0 =C2=A0 =C2=A0sparc64: move cpu_interrupts_enabled to cpu.h > =C2=A0 =C2=A0 =C2=A0sparc64: interrupt trap handling > =C2=A0 =C2=A0 =C2=A0sparc64: reimplement tick timers > > > =C2=A0cpu-exec.c =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | =C2= =A0 28 +++--- > =C2=A0hw/sun4u.c =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | =C2= =A0225 +++++++++++++++++++++++++++++++++++++--------- > =C2=A0target-sparc/cpu.h =C2=A0 =C2=A0 =C2=A0 | =C2=A0 27 ++++++ > =C2=A0target-sparc/exec.h =C2=A0 =C2=A0 =C2=A0| =C2=A0 13 --- > =C2=A0target-sparc/helper.c =C2=A0 =C2=A0| =C2=A0 =C2=A01 > =C2=A0target-sparc/helper.h =C2=A0 =C2=A0| =C2=A0 =C2=A01 > =C2=A0target-sparc/op_helper.c | =C2=A0 81 +++++++++++++++-- > =C2=A0target-sparc/translate.c | =C2=A0 =C2=A05 - > =C2=A08 files changed, 300 insertions(+), 81 deletions(-) > > -- > Kind regards, > Igor V. Kovalenko > > >