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From: Blue Swirl <blauwirbel@gmail.com>
Date: Wed, 27 Jan 2010 21:40:13 +0000
Message-ID: <f43fc5581001271340v58ae9238oc516a0dae20d0810@mail.gmail.com>
Subject: Re: [Qemu-devel] [PATCH] sparc64: reimplement tick timers v4
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To: qemu-devel@nongnu.org

Thanks, applied.


On Wed, Jan 27, 2010 at 9:00 PM, Igor V. Kovalenko
<igor.v.kovalenko@gmail.com> wrote:
> From: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
>
> sparc64 timer has tick counter which can be set and read,
> and tick compare value used as deadline to fire timer interrupt.
> The timer is not used as periodic timer, instead deadline
> is set each time new timer interrupt is needed.
>
> v3 -> v4:
> - coding style
>
> v2 -> v3:
> - added missing timer debug output macro
> - CPUTimer struct and typedef moved to cpu.h
> - change CPU_SAVE_VERSION to 6, older save formats not supported
>
> v1 -> v2:
> - new conversion helpers cpu_to_timer_ticks and timer_to_cpu_ticks
> - save offset from clock source to implement cpu_tick_set_count
> - renamed struct sun4u_timer to CPUTimer
> - load and save cpu timers
>
> v0 -> v1:
> - coding style
>
> Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
> ---
> =C2=A0hw/sun4u.c =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | =C2=A0206 ++=
++++++++++++++++++++++++++++++++++++++--------
> =C2=A0target-sparc/cpu.h =C2=A0 =C2=A0 | =C2=A0 28 +++++--
> =C2=A0target-sparc/machine.c | =C2=A0 14 ++-
> =C2=A03 files changed, 202 insertions(+), 46 deletions(-)
>
> diff --git a/hw/sun4u.c b/hw/sun4u.c
> index c1530a6..1e01123 100644
> --- a/hw/sun4u.c
> +++ b/hw/sun4u.c
> @@ -40,6 +40,7 @@
>
> =C2=A0//#define DEBUG_IRQ
> =C2=A0//#define DEBUG_EBUS
> +//#define DEBUG_TIMER
>
> =C2=A0#ifdef DEBUG_IRQ
> =C2=A0#define CPUIRQ_DPRINTF(fmt, ...) =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=
 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0\
> @@ -55,6 +56,13 @@
> =C2=A0#define EBUS_DPRINTF(fmt, ...)
> =C2=A0#endif
>
> +#ifdef DEBUG_TIMER
> +#define TIMER_DPRINTF(fmt, ...) =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0\
> + =C2=A0 =C2=A0do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0)
> +#else
> +#define TIMER_DPRINTF(fmt, ...)
> +#endif
> +
> =C2=A0#define KERNEL_LOAD_ADDR =C2=A0 =C2=A0 0x00404000
> =C2=A0#define CMDLINE_ADDR =C2=A0 =C2=A0 =C2=A0 =C2=A0 0x003ff000
> =C2=A0#define INITRD_LOAD_ADDR =C2=A0 =C2=A0 0x00300000
> @@ -282,6 +290,12 @@ void cpu_check_irqs(CPUState *env)
> =C2=A0 =C2=A0 }
> =C2=A0}
>
> +static void cpu_kick_irq(CPUState *env)
> +{
> + =C2=A0 =C2=A0env->halted =3D 0;
> + =C2=A0 =C2=A0cpu_check_irqs(env);
> +}
> +
> =C2=A0static void cpu_set_irq(void *opaque, int irq, int level)
> =C2=A0{
> =C2=A0 =C2=A0 CPUState *env =3D opaque;
> @@ -303,6 +317,52 @@ typedef struct ResetData {
> =C2=A0 =C2=A0 uint64_t prom_addr;
> =C2=A0} ResetData;
>
> +void cpu_put_timer(QEMUFile *f, CPUTimer *s)
> +{
> + =C2=A0 =C2=A0qemu_put_be32s(f, &s->frequency);
> + =C2=A0 =C2=A0qemu_put_be32s(f, &s->disabled);
> + =C2=A0 =C2=A0qemu_put_be64s(f, &s->disabled_mask);
> + =C2=A0 =C2=A0qemu_put_sbe64s(f, &s->clock_offset);
> +
> + =C2=A0 =C2=A0qemu_put_timer(f, s->qtimer);
> +}
> +
> +void cpu_get_timer(QEMUFile *f, CPUTimer *s)
> +{
> + =C2=A0 =C2=A0qemu_get_be32s(f, &s->frequency);
> + =C2=A0 =C2=A0qemu_get_be32s(f, &s->disabled);
> + =C2=A0 =C2=A0qemu_get_be64s(f, &s->disabled_mask);
> + =C2=A0 =C2=A0qemu_get_sbe64s(f, &s->clock_offset);
> +
> + =C2=A0 =C2=A0qemu_get_timer(f, s->qtimer);
> +}
> +
> +static CPUTimer* cpu_timer_create(const char* name, CPUState *env,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0QEMUBHFunc *cb, uint32_t fr=
equency,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t disabled_mask)
> +{
> + =C2=A0 =C2=A0CPUTimer *timer =3D qemu_mallocz(sizeof (CPUTimer));
> +
> + =C2=A0 =C2=A0timer->name =3D name;
> + =C2=A0 =C2=A0timer->frequency =3D frequency;
> + =C2=A0 =C2=A0timer->disabled_mask =3D disabled_mask;
> +
> + =C2=A0 =C2=A0timer->disabled =3D 1;
> + =C2=A0 =C2=A0timer->clock_offset =3D qemu_get_clock(vm_clock);
> +
> + =C2=A0 =C2=A0timer->qtimer =3D qemu_new_timer(vm_clock, cb, env);
> +
> + =C2=A0 =C2=A0return timer;
> +}
> +
> +static void cpu_timer_reset(CPUTimer *timer)
> +{
> + =C2=A0 =C2=A0timer->disabled =3D 1;
> + =C2=A0 =C2=A0timer->clock_offset =3D qemu_get_clock(vm_clock);
> +
> + =C2=A0 =C2=A0qemu_del_timer(timer->qtimer);
> +}
> +
> =C2=A0static void main_cpu_reset(void *opaque)
> =C2=A0{
> =C2=A0 =C2=A0 ResetData *s =3D (ResetData *)opaque;
> @@ -310,15 +370,11 @@ static void main_cpu_reset(void *opaque)
> =C2=A0 =C2=A0 static unsigned int nr_resets;
>
> =C2=A0 =C2=A0 cpu_reset(env);
> - =C2=A0 =C2=A0env->tick_cmpr =3D TICK_INT_DIS | 0;
> - =C2=A0 =C2=A0ptimer_set_limit(env->tick, TICK_MAX, 1);
> - =C2=A0 =C2=A0ptimer_run(env->tick, 1);
> - =C2=A0 =C2=A0env->stick_cmpr =3D TICK_INT_DIS | 0;
> - =C2=A0 =C2=A0ptimer_set_limit(env->stick, TICK_MAX, 1);
> - =C2=A0 =C2=A0ptimer_run(env->stick, 1);
> - =C2=A0 =C2=A0env->hstick_cmpr =3D TICK_INT_DIS | 0;
> - =C2=A0 =C2=A0ptimer_set_limit(env->hstick, TICK_MAX, 1);
> - =C2=A0 =C2=A0ptimer_run(env->hstick, 1);
> +
> + =C2=A0 =C2=A0cpu_timer_reset(env->tick);
> + =C2=A0 =C2=A0cpu_timer_reset(env->stick);
> + =C2=A0 =C2=A0cpu_timer_reset(env->hstick);
> +
> =C2=A0 =C2=A0 env->gregs[1] =3D 0; // Memory start
> =C2=A0 =C2=A0 env->gregs[2] =3D ram_size; // Memory size
> =C2=A0 =C2=A0 env->gregs[3] =3D 0; // Machine description XXX
> @@ -335,44 +391,127 @@ static void tick_irq(void *opaque)
> =C2=A0{
> =C2=A0 =C2=A0 CPUState *env =3D opaque;
>
> - =C2=A0 =C2=A0if (!(env->tick_cmpr & TICK_INT_DIS)) {
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0env->softint |=3D SOFTINT_TIMER;
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0cpu_interrupt(env, CPU_INTERRUPT_TIMER);
> + =C2=A0 =C2=A0CPUTimer* timer =3D env->tick;
> +
> + =C2=A0 =C2=A0if (timer->disabled) {
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0CPUIRQ_DPRINTF("tick_irq: softint disabled\n=
");
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0return;
> + =C2=A0 =C2=A0} else {
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0CPUIRQ_DPRINTF("tick: fire\n");
> =C2=A0 =C2=A0 }
> +
> + =C2=A0 =C2=A0env->softint |=3D SOFTINT_TIMER;
> + =C2=A0 =C2=A0cpu_kick_irq(env);
> =C2=A0}
>
> =C2=A0static void stick_irq(void *opaque)
> =C2=A0{
> =C2=A0 =C2=A0 CPUState *env =3D opaque;
>
> - =C2=A0 =C2=A0if (!(env->stick_cmpr & TICK_INT_DIS)) {
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0env->softint |=3D SOFTINT_STIMER;
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0cpu_interrupt(env, CPU_INTERRUPT_TIMER);
> + =C2=A0 =C2=A0CPUTimer* timer =3D env->stick;
> +
> + =C2=A0 =C2=A0if (timer->disabled) {
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0CPUIRQ_DPRINTF("stick_irq: softint disabled\=
n");
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0return;
> + =C2=A0 =C2=A0} else {
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0CPUIRQ_DPRINTF("stick: fire\n");
> =C2=A0 =C2=A0 }
> +
> + =C2=A0 =C2=A0env->softint |=3D SOFTINT_STIMER;
> + =C2=A0 =C2=A0cpu_kick_irq(env);
> =C2=A0}
>
> =C2=A0static void hstick_irq(void *opaque)
> =C2=A0{
> =C2=A0 =C2=A0 CPUState *env =3D opaque;
>
> - =C2=A0 =C2=A0if (!(env->hstick_cmpr & TICK_INT_DIS)) {
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0cpu_interrupt(env, CPU_INTERRUPT_TIMER);
> + =C2=A0 =C2=A0CPUTimer* timer =3D env->hstick;
> +
> + =C2=A0 =C2=A0if (timer->disabled) {
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0CPUIRQ_DPRINTF("hstick_irq: softint disabled=
\n");
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0return;
> + =C2=A0 =C2=A0} else {
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0CPUIRQ_DPRINTF("hstick: fire\n");
> =C2=A0 =C2=A0 }
> +
> + =C2=A0 =C2=A0env->softint |=3D SOFTINT_STIMER;
> + =C2=A0 =C2=A0cpu_kick_irq(env);
> +}
> +
> +static int64_t cpu_to_timer_ticks(int64_t cpu_ticks, uint32_t frequency)
> +{
> + =C2=A0 =C2=A0return muldiv64(cpu_ticks, get_ticks_per_sec(), frequency)=
;
> +}
> +
> +static uint64_t timer_to_cpu_ticks(int64_t timer_ticks, uint32_t frequen=
cy)
> +{
> + =C2=A0 =C2=A0return muldiv64(timer_ticks, frequency, get_ticks_per_sec(=
));
> =C2=A0}
>
> -void cpu_tick_set_count(void *opaque, uint64_t count)
> +void cpu_tick_set_count(CPUTimer *timer, uint64_t count)
> =C2=A0{
> - =C2=A0 =C2=A0ptimer_set_count(opaque, -count);
> + =C2=A0 =C2=A0uint64_t real_count =3D count & ~timer->disabled_mask;
> + =C2=A0 =C2=A0uint64_t disabled_bit =3D count & timer->disabled_mask;
> +
> + =C2=A0 =C2=A0int64_t vm_clock_offset =3D qemu_get_clock(vm_clock) -
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cp=
u_to_timer_ticks(real_count, timer->frequency);
> +
> + =C2=A0 =C2=A0TIMER_DPRINTF("%s set_count count=3D0x%016lx (%s) p=3D%p\n=
",
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0timer->na=
me, real_count,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0timer->di=
sabled?"disabled":"enabled", timer);
> +
> + =C2=A0 =C2=A0timer->disabled =3D disabled_bit ? 1 : 0;
> + =C2=A0 =C2=A0timer->clock_offset =3D vm_clock_offset;
> =C2=A0}
>
> -uint64_t cpu_tick_get_count(void *opaque)
> +uint64_t cpu_tick_get_count(CPUTimer *timer)
> =C2=A0{
> - =C2=A0 =C2=A0return -ptimer_get_count(opaque);
> + =C2=A0 =C2=A0uint64_t real_count =3D timer_to_cpu_ticks(
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0qe=
mu_get_clock(vm_clock) - timer->clock_offset,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ti=
mer->frequency);
> +
> + =C2=A0 =C2=A0TIMER_DPRINTF("%s get_count count=3D0x%016lx (%s) p=3D%p\n=
",
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 timer->name, real_count,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 timer->disabled?"disabled":"enabled"=
, timer);
> +
> + =C2=A0 =C2=A0if (timer->disabled)
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0real_count |=3D timer->disabled_mask;
> +
> + =C2=A0 =C2=A0return real_count;
> =C2=A0}
>
> -void cpu_tick_set_limit(void *opaque, uint64_t limit)
> +void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit)
> =C2=A0{
> - =C2=A0 =C2=A0ptimer_set_limit(opaque, -limit, 0);
> + =C2=A0 =C2=A0int64_t now =3D qemu_get_clock(vm_clock);
> +
> + =C2=A0 =C2=A0uint64_t real_limit =3D limit & ~timer->disabled_mask;
> + =C2=A0 =C2=A0timer->disabled =3D (limit & timer->disabled_mask) ? 1 : 0=
;
> +
> + =C2=A0 =C2=A0int64_t expires =3D cpu_to_timer_ticks(real_limit, timer->=
frequency) +
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ti=
mer->clock_offset;
> +
> + =C2=A0 =C2=A0if (expires < now) {
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0expires =3D now + 1;
> + =C2=A0 =C2=A0}
> +
> + =C2=A0 =C2=A0TIMER_DPRINTF("%s set_limit limit=3D0x%016lx (%s) p=3D%p "
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"called w=
ith limit=3D0x%016lx at 0x%016lx (delta=3D0x%016lx)\n",
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0timer->na=
me, real_limit,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0timer->di=
sabled?"disabled":"enabled",
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0timer, li=
mit,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0timer_to_=
cpu_ticks(now - timer->clock_offset,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 timer->frequency),
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0timer_to_=
cpu_ticks(expires - now, timer->frequency));
> +
> + =C2=A0 =C2=A0if (!real_limit) {
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0TIMER_DPRINTF("%s set_limit limit=3DZERO - n=
ot starting timer\n",
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0timer->name);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_del_timer(timer->qtimer);
> + =C2=A0 =C2=A0} else if (timer->disabled) {
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_del_timer(timer->qtimer);
> + =C2=A0 =C2=A0} else {
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_mod_timer(timer->qtimer, expires);
> + =C2=A0 =C2=A0}
> =C2=A0}
>
> =C2=A0static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
> @@ -559,9 +698,12 @@ device_init(ram_register_devices);
> =C2=A0static CPUState *cpu_devinit(const char *cpu_model, const struct hw=
def *hwdef)
> =C2=A0{
> =C2=A0 =C2=A0 CPUState *env;
> - =C2=A0 =C2=A0QEMUBH *bh;
> =C2=A0 =C2=A0 ResetData *reset_info;
>
> + =C2=A0 =C2=A0uint32_t =C2=A0 tick_frequency =3D 100*1000000;
> + =C2=A0 =C2=A0uint32_t =C2=A0stick_frequency =3D 100*1000000;
> + =C2=A0 =C2=A0uint32_t hstick_frequency =3D 100*1000000;
> +
> =C2=A0 =C2=A0 if (!cpu_model)
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 cpu_model =3D hwdef->default_cpu_model;
> =C2=A0 =C2=A0 env =3D cpu_init(cpu_model);
> @@ -569,17 +711,15 @@ static CPUState *cpu_devinit(const char *cpu_model,=
 const struct hwdef *hwdef)
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 fprintf(stderr, "Unable to find Sparc CPU def=
inition\n");
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 exit(1);
> =C2=A0 =C2=A0 }
> - =C2=A0 =C2=A0bh =3D qemu_bh_new(tick_irq, env);
> - =C2=A0 =C2=A0env->tick =3D ptimer_init(bh);
> - =C2=A0 =C2=A0ptimer_set_period(env->tick, 1ULL);
>
> - =C2=A0 =C2=A0bh =3D qemu_bh_new(stick_irq, env);
> - =C2=A0 =C2=A0env->stick =3D ptimer_init(bh);
> - =C2=A0 =C2=A0ptimer_set_period(env->stick, 1ULL);
> + =C2=A0 =C2=A0env->tick =3D cpu_timer_create("tick", env, tick_irq,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0tick_frequency, TICK_NPT_MA=
SK);
> +
> + =C2=A0 =C2=A0env->stick =3D cpu_timer_create("stick", env, stick_irq,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 stick_frequency, TICK_INT_=
DIS);
>
> - =C2=A0 =C2=A0bh =3D qemu_bh_new(hstick_irq, env);
> - =C2=A0 =C2=A0env->hstick =3D ptimer_init(bh);
> - =C2=A0 =C2=A0ptimer_set_period(env->hstick, 1ULL);
> + =C2=A0 =C2=A0env->hstick =3D cpu_timer_create("hstick", env, hstick_irq=
,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0hstick_frequency, TI=
CK_INT_DIS);
>
> =C2=A0 =C2=A0 reset_info =3D qemu_mallocz(sizeof(ResetData));
> =C2=A0 =C2=A0 reset_info->env =3D env;
> diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
> index 842a2f4..5980deb 100644
> --- a/target-sparc/cpu.h
> +++ b/target-sparc/cpu.h
> @@ -292,6 +292,22 @@ typedef struct SparcTLBEntry {
> =C2=A0 =C2=A0 uint64_t tte;
> =C2=A0} SparcTLBEntry;
>
> +struct CPUTimer
> +{
> + =C2=A0 =C2=A0const char *name;
> + =C2=A0 =C2=A0uint32_t =C2=A0 =C2=A0frequency;
> + =C2=A0 =C2=A0uint32_t =C2=A0 =C2=A0disabled;
> + =C2=A0 =C2=A0uint64_t =C2=A0 =C2=A0disabled_mask;
> + =C2=A0 =C2=A0int64_t =C2=A0 =C2=A0 clock_offset;
> + =C2=A0 =C2=A0struct QEMUTimer =C2=A0*qtimer;
> +};
> +
> +typedef struct CPUTimer CPUTimer;
> +
> +struct QEMUFile;
> +void cpu_put_timer(struct QEMUFile *f, CPUTimer *s);
> +void cpu_get_timer(struct QEMUFile *f, CPUTimer *s);
> +
> =C2=A0typedef struct CPUSPARCState {
> =C2=A0 =C2=A0 target_ulong gregs[8]; /* general registers */
> =C2=A0 =C2=A0 target_ulong *regwptr; /* pointer to current register windo=
w */
> @@ -393,14 +409,14 @@ typedef struct CPUSPARCState {
> =C2=A0 =C2=A0 uint64_t mgregs[8]; /* mmu general registers */
> =C2=A0 =C2=A0 uint64_t fprs;
> =C2=A0 =C2=A0 uint64_t tick_cmpr, stick_cmpr;
> - =C2=A0 =C2=A0void *tick, *stick;
> + =C2=A0 =C2=A0CPUTimer *tick, *stick;
> =C2=A0#define TICK_NPT_MASK =C2=A0 =C2=A0 =C2=A0 =C2=A00x8000000000000000=
ULL
> =C2=A0#define TICK_INT_DIS =C2=A0 =C2=A0 =C2=A0 =C2=A0 0x8000000000000000=
ULL
> =C2=A0 =C2=A0 uint64_t gsr;
> =C2=A0 =C2=A0 uint32_t gl; // UA2005
> =C2=A0 =C2=A0 /* UA 2005 hyperprivileged registers */
> =C2=A0 =C2=A0 uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hs=
tick_cmpr, ssr;
> - =C2=A0 =C2=A0void *hstick; // UA 2005
> + =C2=A0 =C2=A0CPUTimer *hstick; // UA 2005
> =C2=A0 =C2=A0 uint32_t softint;
> =C2=A0#define SOFTINT_TIMER =C2=A0 1
> =C2=A0#define SOFTINT_STIMER =C2=A0(1 << 16)
> @@ -536,7 +552,7 @@ int cpu_sparc_signal_handler(int host_signum, void *p=
info, void *puc);
> =C2=A0#define cpu_signal_handler cpu_sparc_signal_handler
> =C2=A0#define cpu_list sparc_cpu_list
>
> -#define CPU_SAVE_VERSION 5
> +#define CPU_SAVE_VERSION 6
>
> =C2=A0/* MMU modes definitions */
> =C2=A0#define MMU_MODE0_SUFFIX _user
> @@ -615,9 +631,9 @@ static inline void cpu_clone_regs(CPUState *env, targ=
et_ulong newsp)
>
> =C2=A0#ifdef TARGET_SPARC64
> =C2=A0/* sun4u.c */
> -void cpu_tick_set_count(void *opaque, uint64_t count);
> -uint64_t cpu_tick_get_count(void *opaque);
> -void cpu_tick_set_limit(void *opaque, uint64_t limit);
> +void cpu_tick_set_count(CPUTimer *timer, uint64_t count);
> +uint64_t cpu_tick_get_count(CPUTimer *timer);
> +void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit);
> =C2=A0trap_state* cpu_tsptr(CPUState* env);
> =C2=A0#endif
>
> diff --git a/target-sparc/machine.c b/target-sparc/machine.c
> index c7c03b6..4b87ec6 100644
> --- a/target-sparc/machine.c
> +++ b/target-sparc/machine.c
> @@ -84,8 +84,8 @@ void cpu_save(QEMUFile *f, void *opaque)
> =C2=A0 =C2=A0 qemu_put_be64s(f, &env->fprs);
> =C2=A0 =C2=A0 qemu_put_be64s(f, &env->tick_cmpr);
> =C2=A0 =C2=A0 qemu_put_be64s(f, &env->stick_cmpr);
> - =C2=A0 =C2=A0qemu_put_ptimer(f, env->tick);
> - =C2=A0 =C2=A0qemu_put_ptimer(f, env->stick);
> + =C2=A0 =C2=A0cpu_put_timer(f, env->tick);
> + =C2=A0 =C2=A0cpu_put_timer(f, env->stick);
> =C2=A0 =C2=A0 qemu_put_be64s(f, &env->gsr);
> =C2=A0 =C2=A0 qemu_put_be32s(f, &env->gl);
> =C2=A0 =C2=A0 qemu_put_be64s(f, &env->hpstate);
> @@ -96,7 +96,7 @@ void cpu_save(QEMUFile *f, void *opaque)
> =C2=A0 =C2=A0 qemu_put_be64s(f, &env->hver);
> =C2=A0 =C2=A0 qemu_put_be64s(f, &env->hstick_cmpr);
> =C2=A0 =C2=A0 qemu_put_be64s(f, &env->ssr);
> - =C2=A0 =C2=A0qemu_put_ptimer(f, env->hstick);
> + =C2=A0 =C2=A0cpu_put_timer(f, env->hstick);
> =C2=A0#endif
> =C2=A0}
>
> @@ -106,7 +106,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_i=
d)
> =C2=A0 =C2=A0 int i;
> =C2=A0 =C2=A0 uint32_t tmp;
>
> - =C2=A0 =C2=A0if (version_id !=3D 5)
> + =C2=A0 =C2=A0if (version_id < 6)
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 return -EINVAL;
> =C2=A0 =C2=A0 for(i =3D 0; i < 8; i++)
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_get_betls(f, &env->gregs[i]);
> @@ -180,8 +180,8 @@ int cpu_load(QEMUFile *f, void *opaque, int version_i=
d)
> =C2=A0 =C2=A0 qemu_get_be64s(f, &env->fprs);
> =C2=A0 =C2=A0 qemu_get_be64s(f, &env->tick_cmpr);
> =C2=A0 =C2=A0 qemu_get_be64s(f, &env->stick_cmpr);
> - =C2=A0 =C2=A0qemu_get_ptimer(f, env->tick);
> - =C2=A0 =C2=A0qemu_get_ptimer(f, env->stick);
> + =C2=A0 =C2=A0cpu_get_timer(f, env->tick);
> + =C2=A0 =C2=A0cpu_get_timer(f, env->stick);
> =C2=A0 =C2=A0 qemu_get_be64s(f, &env->gsr);
> =C2=A0 =C2=A0 qemu_get_be32s(f, &env->gl);
> =C2=A0 =C2=A0 qemu_get_be64s(f, &env->hpstate);
> @@ -192,7 +192,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_i=
d)
> =C2=A0 =C2=A0 qemu_get_be64s(f, &env->hver);
> =C2=A0 =C2=A0 qemu_get_be64s(f, &env->hstick_cmpr);
> =C2=A0 =C2=A0 qemu_get_be64s(f, &env->ssr);
> - =C2=A0 =C2=A0qemu_get_ptimer(f, env->hstick);
> + =C2=A0 =C2=A0cpu_get_timer(f, env->hstick);
> =C2=A0#endif
> =C2=A0 =C2=A0 tlb_flush(env, 1);
> =C2=A0 =C2=A0 return 0;
>
>
>
>