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From: Blue Swirl <blauwirbel@gmail.com>
Date: Wed, 27 Jan 2010 21:51:44 +0000
Message-ID: <f43fc5581001271351q615a832fh65775861ade5225f@mail.gmail.com>
Subject: Re: [Qemu-devel] [PATCH] sparc64: reimplement tick timers v4
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To: "Igor V. Kovalenko" <igor.v.kovalenko@gmail.com>
Cc: qemu-devel@nongnu.org

On Wed, Jan 27, 2010 at 9:00 PM, Igor V. Kovalenko
<igor.v.kovalenko@gmail.com> wrote:
> From: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
>
> sparc64 timer has tick counter which can be set and read,
> and tick compare value used as deadline to fire timer interrupt.
> The timer is not used as periodic timer, instead deadline
> is set each time new timer interrupt is needed.

Now also IDE probe succeeds, almost:

cmd64x 0000:00:05.0: IDE controller (0x1095:0x0646 rev 0x07)
cmd64x 0000:00:05.0: 100% native mode on irq 1
    ide0: BM-DMA at 0x1fe02000700-0x1fe02000707
    ide1: BM-DMA at 0x1fe02000708-0x1fe0200070f
hdc: EQUMD DVR-MO, ATAPI cdrom or floppy?, assuming FLOPPY drive
ide0 at 0x1fe02000500-0x1fe02000507,0x1fe02000582 on irq 1 (serialized)
ide1 at 0x1fe02000600-0x1fe02000607,0x1fe02000682 on irq 1 (serialized)
ide-gd driver 1.18