From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Ng1hx-0000rF-0n for qemu-devel@nongnu.org; Fri, 12 Feb 2010 15:01:45 -0500 Received: from [199.232.76.173] (port=44294 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Ng1hw-0000r6-Mz for qemu-devel@nongnu.org; Fri, 12 Feb 2010 15:01:44 -0500 Received: from Debian-exim by monty-python.gnu.org with spam-scanned (Exim 4.60) (envelope-from ) id 1Ng1hv-0007XU-9n for qemu-devel@nongnu.org; Fri, 12 Feb 2010 15:01:44 -0500 Received: from mail-pz0-f187.google.com ([209.85.222.187]:45772) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1Ng1hu-0007XI-Ny for qemu-devel@nongnu.org; Fri, 12 Feb 2010 15:01:43 -0500 Received: by pzk17 with SMTP id 17so1670218pzk.4 for ; Fri, 12 Feb 2010 12:01:41 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <4375b210e2ec2400c7bd1294d85d1099bcc1385d.1265933757.git.rth@twiddle.net> References: <4375b210e2ec2400c7bd1294d85d1099bcc1385d.1265933757.git.rth@twiddle.net> From: Blue Swirl Date: Fri, 12 Feb 2010 22:01:21 +0200 Message-ID: Subject: Re: [Qemu-devel] [PATCH 1/6] Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h. Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: qemu-devel@nongnu.org On Fri, Feb 12, 2010 at 12:20 AM, Richard Henderson wrote= : > Removes a set of ifdefs from exec.c. > > Introduce TARGET_VIRT_ADDR_SPACE_BITS for all targets other > than Alpha. =C2=A0This will be used for page_find_alloc, which is > supposed to be using virtual addresses in the first place. > --- > =C2=A0exec.c =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0| =C2=A0 17 ----------------- > =C2=A0target-alpha/cpu.h =C2=A0 =C2=A0 =C2=A0| =C2=A0 =C2=A04 +++- > =C2=A0target-arm/cpu.h =C2=A0 =C2=A0 =C2=A0 =C2=A0| =C2=A0 =C2=A03 +++ > =C2=A0target-cris/cpu.h =C2=A0 =C2=A0 =C2=A0 | =C2=A0 =C2=A03 +++ > =C2=A0target-i386/cpu.h =C2=A0 =C2=A0 =C2=A0 | =C2=A0 11 +++++++++++ > =C2=A0target-m68k/cpu.h =C2=A0 =C2=A0 =C2=A0 | =C2=A0 =C2=A03 +++ > =C2=A0target-microblaze/cpu.h | =C2=A0 =C2=A03 +++ > =C2=A0target-mips/mips-defs.h | =C2=A0 =C2=A04 ++++ > =C2=A0target-ppc/cpu.h =C2=A0 =C2=A0 =C2=A0 =C2=A0| =C2=A0 17 +++++++++++= ++++++ > =C2=A0target-s390x/cpu.h =C2=A0 =C2=A0 =C2=A0| =C2=A0 =C2=A05 +++++ > =C2=A0target-sh4/cpu.h =C2=A0 =C2=A0 =C2=A0 =C2=A0| =C2=A0 =C2=A03 +++ > =C2=A0target-sparc/cpu.h =C2=A0 =C2=A0 =C2=A0| =C2=A0 =C2=A08 ++++++++ > =C2=A012 files changed, 63 insertions(+), 18 deletions(-) > > diff --git a/exec.c b/exec.c > index 8389c54..766568b 100644 > --- a/exec.c > +++ b/exec.c > @@ -62,23 +62,6 @@ > > =C2=A0#define SMC_BITMAP_USE_THRESHOLD 10 > > -#if defined(TARGET_SPARC64) > -#define TARGET_PHYS_ADDR_SPACE_BITS 41 > -#elif defined(TARGET_SPARC) > -#define TARGET_PHYS_ADDR_SPACE_BITS 36 > -#elif defined(TARGET_ALPHA) > -#define TARGET_PHYS_ADDR_SPACE_BITS 42 > -#define TARGET_VIRT_ADDR_SPACE_BITS 42 > -#elif defined(TARGET_PPC64) > -#define TARGET_PHYS_ADDR_SPACE_BITS 42 > -#elif defined(TARGET_X86_64) > -#define TARGET_PHYS_ADDR_SPACE_BITS 42 > -#elif defined(TARGET_I386) > -#define TARGET_PHYS_ADDR_SPACE_BITS 36 > -#else > -#define TARGET_PHYS_ADDR_SPACE_BITS 32 > -#endif > - > =C2=A0static TranslationBlock *tbs; > =C2=A0int code_gen_max_blocks; > =C2=A0TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; > diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h > index c0dff4b..c144b4b 100644 > --- a/target-alpha/cpu.h > +++ b/target-alpha/cpu.h > @@ -41,7 +41,9 @@ > > =C2=A0#define TARGET_PAGE_BITS 13 > > -#define VA_BITS 43 > +/* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44. =C2=A0*/ > +#define TARGET_PHYS_ADDR_SPACE_BITS =C2=A0 =C2=A044 > +#define TARGET_VIRT_ADDR_SPACE_BITS =C2=A0 =C2=A0(30 + TARGET_PAGE_BITS) > > =C2=A0/* Alpha major type */ > =C2=A0enum { > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index 4a1c53f..3892db4 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -405,6 +405,9 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, > =C2=A0#define TARGET_PAGE_BITS 10 > =C2=A0#endif > > +#define TARGET_PHYS_ADDR_SPACE_BITS 32 > +#define TARGET_VIRT_ADDR_SPACE_BITS 32 > + > =C2=A0#define cpu_init cpu_arm_init > =C2=A0#define cpu_exec cpu_arm_exec > =C2=A0#define cpu_gen_code cpu_arm_gen_code > diff --git a/target-cris/cpu.h b/target-cris/cpu.h > index 0626cd8..26171ca 100644 > --- a/target-cris/cpu.h > +++ b/target-cris/cpu.h > @@ -195,6 +195,9 @@ enum { > =C2=A0#define TARGET_PAGE_BITS 13 > =C2=A0#define MMAP_SHIFT TARGET_PAGE_BITS > > +#define TARGET_PHYS_ADDR_SPACE_BITS 32 > +#define TARGET_VIRT_ADDR_SPACE_BITS 32 > + > =C2=A0#define cpu_init cpu_cris_init > =C2=A0#define cpu_exec cpu_cris_exec > =C2=A0#define cpu_gen_code cpu_cris_gen_code > diff --git a/target-i386/cpu.h b/target-i386/cpu.h > index 216b00e..7fb84db 100644 > --- a/target-i386/cpu.h > +++ b/target-i386/cpu.h > @@ -872,6 +872,17 @@ uint64_t cpu_get_tsc(CPUX86State *env); > > =C2=A0#define TARGET_PAGE_BITS 12 > > +#ifdef TARGET_X86_64 > +#define TARGET_PHYS_ADDR_SPACE_BITS 52 > +/* ??? This is really 48 bits, sign-extended, but the only thing > + =C2=A0 accessible to userland with bit 48 set is the VSYSCALL, and that > + =C2=A0 is handled via other mechanisms. =C2=A0*/ > +#define TARGET_VIRT_ADDR_SPACE_BITS 47 > +#else > +#define TARGET_PHYS_ADDR_SPACE_BITS 36 > +#define TARGET_VIRT_ADDR_SPACE_BITS 32 > +#endif > + > =C2=A0#define cpu_init cpu_x86_init > =C2=A0#define cpu_exec cpu_x86_exec > =C2=A0#define cpu_gen_code cpu_x86_gen_code > diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h > index 68a7e41..b2f37ec 100644 > --- a/target-m68k/cpu.h > +++ b/target-m68k/cpu.h > @@ -210,6 +210,9 @@ void register_m68k_insns (CPUM68KState *env); > =C2=A0#define TARGET_PAGE_BITS 10 > =C2=A0#endif > > +#define TARGET_PHYS_ADDR_SPACE_BITS 32 > +#define TARGET_VIRT_ADDR_SPACE_BITS 32 > + > =C2=A0#define cpu_init cpu_m68k_init > =C2=A0#define cpu_exec cpu_m68k_exec > =C2=A0#define cpu_gen_code cpu_m68k_gen_code > diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h > index 1bf4875..5999386 100644 > --- a/target-microblaze/cpu.h > +++ b/target-microblaze/cpu.h > @@ -253,6 +253,9 @@ enum { > =C2=A0#define TARGET_PAGE_BITS 12 > =C2=A0#define MMAP_SHIFT TARGET_PAGE_BITS > > +#define TARGET_PHYS_ADDR_SPACE_BITS 32 > +#define TARGET_VIRT_ADDR_SPACE_BITS 32 > + > =C2=A0#define cpu_init cpu_mb_init > =C2=A0#define cpu_exec cpu_mb_exec > =C2=A0#define cpu_gen_code cpu_mb_gen_code > diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h > index 54e80f1..0f6a956 100644 > --- a/target-mips/mips-defs.h > +++ b/target-mips/mips-defs.h > @@ -8,6 +8,10 @@ > =C2=A0#define TARGET_PAGE_BITS 12 > =C2=A0#define MIPS_TLB_MAX 128 > > +/* ??? MIPS64 no doubt has a larger address space. =C2=A0*/ > +#define TARGET_PHYS_ADDR_SPACE_BITS 32 > +#define TARGET_VIRT_ADDR_SPACE_BITS 32 > + > =C2=A0#if defined(TARGET_MIPS64) > =C2=A0#define TARGET_LONG_BITS 64 > =C2=A0#else > diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h > index d15bba1..c91f8fe 100644 > --- a/target-ppc/cpu.h > +++ b/target-ppc/cpu.h > @@ -29,6 +29,20 @@ > =C2=A0#define TARGET_LONG_BITS 64 > =C2=A0#define TARGET_PAGE_BITS 12 > > +/* Note that the official physical address space bits is 62-M where M > + =C2=A0 is implementation dependent. =C2=A0I've not looked up M for the = set of > + =C2=A0 cpus we emulate at the system level. =C2=A0*/ > +#define TARGET_PHYS_ADDR_SPACE_BITS 62 > + > +/* Note that the PPC environment architecture talks about 80 bit virtual > + =C2=A0 addresses, with segmentation. =C2=A0Obviously that's not all vis= ible to a > + =C2=A0 single process, which is all we're concerned with here. =C2=A0*/ > +#ifdef TARGET_ABI32 > +# define TARGET_VIRT_ADDR_SPACE_BITS 32 > +#else > +# define TARGET_VIRT_ADDR_SPACE_BITS 64 > +#endif I'd suppose this change applies to all targets with ABI32, not just PPC. > + > =C2=A0#else /* defined (TARGET_PPC64) */ > =C2=A0/* PowerPC 32 definitions */ > =C2=A0#define TARGET_LONG_BITS 32 > @@ -50,6 +64,9 @@ > =C2=A0#define TARGET_PAGE_BITS 12 > =C2=A0#endif /* defined(TARGET_PPCEMB) */ > > +#define TARGET_PHYS_ADDR_SPACE_BITS 32 > +#define TARGET_VIRT_ADDR_SPACE_BITS 32 > + > =C2=A0#endif /* defined (TARGET_PPC64) */ > > =C2=A0#define CPUState struct CPUPPCState > diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h > index 0e75e1c..56fc083 100644 > --- a/target-s390x/cpu.h > +++ b/target-s390x/cpu.h > @@ -100,6 +100,11 @@ int cpu_s390x_handle_mmu_fault (CPUS390XState *env, = target_ulong address, int rw > > =C2=A0#define TARGET_PAGE_BITS 12 > > +/* ??? This is certainly wrong for 64-bit s390x, but given that only KVM > + =C2=A0 emulation actually works, this is good enough for a placeholder.= =C2=A0*/ > +#define TARGET_PHYS_ADDR_SPACE_BITS 32 > +#define TARGET_VIRT_ADDR_SPACE_BITS 32 > + > =C2=A0#ifndef CONFIG_USER_ONLY > =C2=A0extern int s390_virtio_hypercall(CPUState *env); > =C2=A0extern void kvm_s390_virtio_irq(CPUState *env, int config_change, u= int64_t token); > diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h > index 85f221d..18a5532 100644 > --- a/target-sh4/cpu.h > +++ b/target-sh4/cpu.h > @@ -44,6 +44,9 @@ > > =C2=A0#define TARGET_PAGE_BITS 12 =C2=A0 =C2=A0/* 4k XXXXX */ > > +#define TARGET_PHYS_ADDR_SPACE_BITS 32 > +#define TARGET_VIRT_ADDR_SPACE_BITS 32 > + > =C2=A0#define SR_MD (1 << 30) > =C2=A0#define SR_RB (1 << 29) > =C2=A0#define SR_BL (1 << 28) > diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h > index 5980deb..a9d61f6 100644 > --- a/target-sparc/cpu.h > +++ b/target-sparc/cpu.h > @@ -7,10 +7,18 @@ > =C2=A0#define TARGET_LONG_BITS 32 > =C2=A0#define TARGET_FPREGS 32 > =C2=A0#define TARGET_PAGE_BITS 12 /* 4k */ > + > +#define TARGET_PHYS_ADDR_SPACE_BITS 41 > + > +/* ??? This is a guess based on PAGE_OFFSET in the Linux kernel. =C2=A0*= / > +#define TARGET_VIRT_ADDR_SPACE_BITS 41 No need to guess, the value for UltraSparc IIi is 44. > + > =C2=A0#else > =C2=A0#define TARGET_LONG_BITS 64 > =C2=A0#define TARGET_FPREGS 64 > =C2=A0#define TARGET_PAGE_BITS 13 /* 8k */ > +#define TARGET_PHYS_ADDR_SPACE_BITS 32 No. Please use the original value. > +#define TARGET_VIRT_ADDR_SPACE_BITS 32 > =C2=A0#endif > > =C2=A0#define CPUState struct CPUSPARCState > -- > 1.6.6 > > > >