From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Nh5kc-00067h-R3 for qemu-devel@nongnu.org; Mon, 15 Feb 2010 13:32:54 -0500 Received: from [199.232.76.173] (port=52018 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Nh5kc-00067V-GM for qemu-devel@nongnu.org; Mon, 15 Feb 2010 13:32:54 -0500 Received: from Debian-exim by monty-python.gnu.org with spam-scanned (Exim 4.60) (envelope-from ) id 1Nh5kb-0007bt-JG for qemu-devel@nongnu.org; Mon, 15 Feb 2010 13:32:54 -0500 Received: from mail-pz0-f187.google.com ([209.85.222.187]:38835) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1Nh5kb-0007bj-5F for qemu-devel@nongnu.org; Mon, 15 Feb 2010 13:32:53 -0500 Received: by pzk17 with SMTP id 17so4222556pzk.4 for ; Mon, 15 Feb 2010 10:32:48 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <1266255590-1327-1-git-send-email-atar4qemu@google.com> References: <1266255590-1327-1-git-send-email-atar4qemu@google.com> From: Blue Swirl Date: Mon, 15 Feb 2010 20:32:28 +0200 Message-ID: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] Re: sparc32 fix spurious dma interrupts v2 List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Artyom Tarasenko Cc: qemu-devel@nongnu.org, Artyom Tarasenko Thanks, applied. On Mon, Feb 15, 2010 at 7:39 PM, Artyom Tarasenko wrote: > Don't raise irq when not enabled. > Raise irq on enabling if DMA_INTR is set > Don't clear irq unless it was raised by DMA, as there are other irq sourc= es > Don't set DMA_INTR bit spuriously. > > v1->v2: > =C2=A0- Don't clear irq unless it was raised by DMA > =C2=A0- Raise irq on enabling if DMA_INTR is set > =C2=A0- Assume revertion of 787cfbc432bf1d353a77cbdb613754f3963371a3 > > Signed-off-by: Artyom Tarasenko > --- > diff --git a/hw/sparc32_dma.c b/hw/sparc32_dma.c > index faf6dbc..18ba035 100644 > --- a/hw/sparc32_dma.c > +++ b/hw/sparc32_dma.c > @@ -3,6 +3,9 @@ > =C2=A0* > =C2=A0* Copyright (c) 2006 Fabrice Bellard > =C2=A0* > + * Modifications: > + * =C2=A02010-Feb-14 Artyom Tarasenko : reworked irq generation > + * > =C2=A0* Permission is hereby granted, free of charge, to any person obtai= ning a copy > =C2=A0* of this software and associated documentation files (the "Softwar= e"), to deal > =C2=A0* in the Software without restriction, including without limitation= the rights > @@ -125,13 +128,19 @@ static void dma_set_irq(void *opaque, int irq, int = level) > =C2=A0{ > =C2=A0 =C2=A0 DMAState *s =3D opaque; > =C2=A0 =C2=A0 if (level) { > - =C2=A0 =C2=A0 =C2=A0 =C2=A0DPRINTF("Raise IRQ\n"); > =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->dmaregs[0] |=3D DMA_INTR; > - =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_irq_raise(s->irq); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0if (s->dmaregs[0] & DMA_INTREN) { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0DPRINTF("Raise IRQ\n"); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_irq_raise(s->irq); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0} > =C2=A0 =C2=A0 } else { > - =C2=A0 =C2=A0 =C2=A0 =C2=A0s->dmaregs[0] &=3D ~DMA_INTR; > - =C2=A0 =C2=A0 =C2=A0 =C2=A0DPRINTF("Lower IRQ\n"); > - =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_irq_lower(s->irq); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0if (s->dmaregs[0] & DMA_INTR) { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0s->dmaregs[0] &=3D ~DMA_INTR; > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (s->dmaregs[0] & DMA_INTREN= ) { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0DPRINTF("Lower I= RQ\n"); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_irq_lower(s= ->irq); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0} > + =C2=A0 =C2=A0 =C2=A0 =C2=A0} > =C2=A0 =C2=A0 } > =C2=A0} > > @@ -142,7 +151,6 @@ void espdma_memory_read(void *opaque, uint8_t *buf, i= nt len) > =C2=A0 =C2=A0 DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n", > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->dmaregs[0] & DMA_WRITE_MEM ?= 'w': 'r', s->dmaregs[1]); > =C2=A0 =C2=A0 sparc_iommu_memory_read(s->iommu, s->dmaregs[1], buf, len); > - =C2=A0 =C2=A0s->dmaregs[0] |=3D DMA_INTR; > =C2=A0 =C2=A0 s->dmaregs[1] +=3D len; > =C2=A0} > > @@ -153,7 +161,6 @@ void espdma_memory_write(void *opaque, uint8_t *buf, = int len) > =C2=A0 =C2=A0 DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n", > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->dmaregs[0] & DMA_WRITE_MEM ?= 'w': 'r', s->dmaregs[1]); > =C2=A0 =C2=A0 sparc_iommu_memory_write(s->iommu, s->dmaregs[1], buf, len)= ; > - =C2=A0 =C2=A0s->dmaregs[0] |=3D DMA_INTR; > =C2=A0 =C2=A0 s->dmaregs[1] +=3D len; > =C2=A0} > > @@ -179,9 +186,16 @@ static void dma_mem_writel(void *opaque, target_phys= _addr_t addr, uint32_t val) > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->dmaregs[saddr], val); > =C2=A0 =C2=A0 switch (saddr) { > =C2=A0 =C2=A0 case 0: > - =C2=A0 =C2=A0 =C2=A0 =C2=A0if (!(val & DMA_INTREN)) { > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0DPRINTF("Lower IRQ\n"); > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_irq_lower(s->irq); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0if (val & DMA_INTREN) { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (val & DMA_INTR) { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0DPRINTF("Raise I= RQ\n"); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_irq_raise(s= ->irq); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0} > + =C2=A0 =C2=A0 =C2=A0 =C2=A0} else { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (s->dmaregs[0] & (DMA_INTR = | DMA_INTREN)) { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0DPRINTF("Lower I= RQ\n"); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_irq_lower(s= ->irq); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0} > =C2=A0 =C2=A0 =C2=A0 =C2=A0 } > =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (val & DMA_RESET) { > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_irq_raise(s->dev_reset); >