From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NhoIv-00046i-S6 for qemu-devel@nongnu.org; Wed, 17 Feb 2010 13:07:17 -0500 Received: from [199.232.76.173] (port=52859 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NhoIv-00046a-I5 for qemu-devel@nongnu.org; Wed, 17 Feb 2010 13:07:17 -0500 Received: from Debian-exim by monty-python.gnu.org with spam-scanned (Exim 4.60) (envelope-from ) id 1NhoIu-0001qH-60 for qemu-devel@nongnu.org; Wed, 17 Feb 2010 13:07:17 -0500 Received: from mail-pw0-f45.google.com ([209.85.160.45]:60330) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NhoIt-0001qB-NG for qemu-devel@nongnu.org; Wed, 17 Feb 2010 13:07:16 -0500 Received: by pwi4 with SMTP id 4so1105789pwi.4 for ; Wed, 17 Feb 2010 10:07:14 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <4B79BB33.2080803@twiddle.net> References: <083a0c3b5513cdecbed907b80a64aa4647de9138.1265751626.git.rth@twiddle.net> <4B79BB33.2080803@twiddle.net> From: Blue Swirl Date: Wed, 17 Feb 2010 20:06:54 +0200 Message-ID: Subject: Re: [Qemu-devel] Re: [PATCH 2/2] tcg-sparc: Implement setcond, setcond2. Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: qemu-devel@nongnu.org Thanks, applied. Please remember the Signed-off-by: line. On Mon, Feb 15, 2010 at 11:22 PM, Richard Henderson wrote= : > On 02/13/2010 02:01 PM, Blue Swirl wrote: >> On Tue, Feb 9, 2010 at 11:37 PM, Richard Henderson wro= te: >>> --- >>> =C2=A0tcg/sparc/tcg-target.c | =C2=A0126 ++++++++++++++++++++++++++++++= ++++++++++++++++++ >>> =C2=A01 files changed, 126 insertions(+), 0 deletions(-) >> >> Something's wrong with the patch... > > Oops. =C2=A0The tree wasn't properly committed when I > extracted the patch. =C2=A0Here's that last again. > > > r~ > --- > commit 8f76ac8882ff2b0d9db402352b9cf632cc92f84f > Author: Richard Henderson > Date: =C2=A0 Mon Feb 15 13:19:49 2010 -0800 > > =C2=A0 =C2=A0tcg-sparc: Implement setcond, setcond2. > > diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c > index dd7a598..5b4347a 100644 > --- a/tcg/sparc/tcg-target.c > +++ b/tcg/sparc/tcg-target.c > @@ -194,6 +194,7 @@ static inline int tcg_target_const_match(tcg_target_l= ong val, > =C2=A0#define INSN_RS2(x) (x) > =C2=A0#define INSN_ASI(x) ((x) << 5) > > +#define INSN_IMM11(x) ((1 << 13) | ((x) & 0x7ff)) > =C2=A0#define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff)) > =C2=A0#define INSN_OFF19(x) (((x) >> 2) & 0x07ffff) > =C2=A0#define INSN_OFF22(x) (((x) >> 2) & 0x3fffff) > @@ -217,6 +218,9 @@ static inline int tcg_target_const_match(tcg_target_l= ong val, > =C2=A0#define COND_VC =C2=A0 =C2=A00xf > =C2=A0#define BA =C2=A0 =C2=A0 =C2=A0 =C2=A0 (INSN_OP(0) | INSN_COND(COND= _A, 0) | INSN_OP2(0x2)) > > +#define MOVCC_ICC =C2=A0(1 << 18) > +#define MOVCC_XCC =C2=A0(1 << 18 | 1 << 12) > + > =C2=A0#define ARITH_ADD =C2=A0(INSN_OP(2) | INSN_OP3(0x00)) > =C2=A0#define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10)) > =C2=A0#define ARITH_AND =C2=A0(INSN_OP(2) | INSN_OP3(0x01)) > @@ -233,6 +237,7 @@ static inline int tcg_target_const_match(tcg_target_l= ong val, > =C2=A0#define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09)) > =C2=A0#define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d)) > =C2=A0#define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d)) > +#define ARITH_MOVCC (INSN_OP(2) | INSN_OP3(0x2c)) > > =C2=A0#define SHIFT_SLL =C2=A0(INSN_OP(2) | INSN_OP3(0x25)) > =C2=A0#define SHIFT_SRL =C2=A0(INSN_OP(2) | INSN_OP3(0x26)) > @@ -580,6 +585,109 @@ static void tcg_out_brcond2_i32(TCGContext *s, int = cond, > =C2=A0} > =C2=A0#endif > > +static void tcg_out_setcond_i32(TCGContext *s, int cond, TCGArg ret, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0TCGArg c1, TCGArg c2, int c2const) > +{ > + =C2=A0 =C2=A0TCGArg t; > + > + =C2=A0 =C2=A0/* For 32-bit comparisons, we can play games with ADDX/SUB= X. =C2=A0*/ > + =C2=A0 =C2=A0switch (cond) { > + =C2=A0 =C2=A0case TCG_COND_EQ: > + =C2=A0 =C2=A0case TCG_COND_NE: > + =C2=A0 =C2=A0 =C2=A0 =C2=A0if (c2 !=3D 0) { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_out_arithc(s, ret, c1, c2,= c2const, ARITH_XOR); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0} > + =C2=A0 =C2=A0 =C2=A0 =C2=A0c1 =3D TCG_REG_G0, c2 =3D ret, c2const =3D 0= ; > + =C2=A0 =C2=A0 =C2=A0 =C2=A0cond =3D (cond =3D=3D TCG_COND_EQ ? TCG_COND= _LEU : TCG_COND_LTU); > + =C2=A0 =C2=A0 =C2=A0 break; > + > + =C2=A0 =C2=A0case TCG_COND_GTU: > + =C2=A0 =C2=A0case TCG_COND_GEU: > + =C2=A0 =C2=A0 =C2=A0 =C2=A0if (c2const && c2 !=3D 0) { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_out_movi_imm13(s, TCG_REG_= I5, c2); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0c2 =3D TCG_REG_I5; > + =C2=A0 =C2=A0 =C2=A0 =C2=A0} > + =C2=A0 =C2=A0 =C2=A0 =C2=A0t =3D c1, c1 =3D c2, c2 =3D t, c2const =3D 0= ; > + =C2=A0 =C2=A0 =C2=A0 =C2=A0cond =3D tcg_swap_cond(cond); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0break; > + > + =C2=A0 =C2=A0case TCG_COND_LTU: > + =C2=A0 =C2=A0case TCG_COND_LEU: > + =C2=A0 =C2=A0 =C2=A0 =C2=A0break; > + > + =C2=A0 =C2=A0default: > + =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_out_cmp(s, c1, c2, c2const); > +#if defined(__sparc_v9__) || defined(__sparc_v8plus__) > + =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_out_movi_imm13(s, ret, 0); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_out32 (s, ARITH_MOVCC | INSN_RD(ret) > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | INSN_R= S1(tcg_cond_to_bcond[cond]) > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | MOVCC_= ICC | INSN_IMM11(1)); > +#else > + =C2=A0 =C2=A0 =C2=A0 =C2=A0t =3D gen_new_label(); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_out_branch_i32(s, INSN_COND(tcg_cond_to_= bcond[cond], 1), t); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_out_movi_imm13(s, ret, 1); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_out_movi_imm13(s, ret, 0); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_out_label(s, t, (tcg_target_long)s->code= _ptr); > +#endif > + =C2=A0 =C2=A0 =C2=A0 =C2=A0return; > + =C2=A0 =C2=A0} > + > + =C2=A0 =C2=A0tcg_out_cmp(s, c1, c2, c2const); > + =C2=A0 =C2=A0if (cond =3D=3D TCG_COND_LTU) { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_out_arithi(s, ret, TCG_REG_G0, 0, ARITH_= ADDX); > + =C2=A0 =C2=A0} else { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_out_arithi(s, ret, TCG_REG_G0, -1, ARITH= _SUBX); > + =C2=A0 =C2=A0} > +} > + > +#if TCG_TARGET_REG_BITS =3D=3D 64 > +static void tcg_out_setcond_i64(TCGContext *s, int cond, TCGArg ret, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0TCGArg c1, TCGArg c2, int c2const) > +{ > + =C2=A0 =C2=A0tcg_out_cmp(s, c1, c2, c2const); > + =C2=A0 =C2=A0tcg_out_movi_imm13(s, ret, 0); > + =C2=A0 =C2=A0tcg_out32 (s, ARITH_MOVCC | INSN_RD(ret) > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | INSN_RS1(tcg_cond_to= _bcond[cond]) > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | MOVCC_XCC | INSN_IMM= 11(1)); > +} > +#else > +static void tcg_out_setcond2_i32(TCGContext *s, int cond, TCGArg ret, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 TCGArg al, TCGArg ah, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 TCGArg bl, int blconst, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 TCGArg bh, int bhconst) > +{ > + =C2=A0 =C2=A0int lab; > + > + =C2=A0 =C2=A0switch (cond) { > + =C2=A0 =C2=A0case TCG_COND_EQ: > + =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_out_setcond_i32(s, TCG_COND_EQ, TCG_REG_= I5, al, bl, blconst); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_out_setcond_i32(s, TCG_COND_EQ, ret, ah,= bh, bhconst); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_out_arith(s, ret, ret, TCG_REG_I5, ARITH= _AND); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0break; > + > + =C2=A0 =C2=A0case TCG_COND_NE: > + =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_out_setcond_i32(s, TCG_COND_NE, TCG_REG_= I5, al, al, blconst); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_out_setcond_i32(s, TCG_COND_NE, ret, ah,= bh, bhconst); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_out_arith(s, ret, ret, TCG_REG_I5, ARITH= _OR); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0break; > + > + =C2=A0 =C2=A0default: > + =C2=A0 =C2=A0 =C2=A0 =C2=A0lab =3D gen_new_label(); > + > + =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_out_cmp(s, ah, bh, bhconst); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_out_branch_i32(s, INSN_COND(tcg_cond_to_= bcond[cond], 1), lab); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_out_movi_imm13(s, ret, 1); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_out_branch_i32(s, INSN_COND(COND_NE, 1),= lab); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_out_movi_imm13(s, ret, 0); > + > + =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_out_setcond_i32(s, tcg_unsigned_cond(con= d), ret, al, bl, blconst); > + > + =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_out_label(s, lab, (tcg_target_long)s->co= de_ptr); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0break; > + =C2=A0 =C2=A0} > +} > +#endif > + > =C2=A0/* Generate global QEMU prologue and epilogue code */ > =C2=A0void tcg_target_qemu_prologue(TCGContext *s) > =C2=A0{ > @@ -1146,12 +1254,22 @@ static inline void tcg_out_op(TCGContext *s, int = opc, const TCGArg *args, > =C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_out_brcond_i32(s, args[2], args[0], args[= 1], const_args[1], > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0args[3]); > =C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > + =C2=A0 =C2=A0case INDEX_op_setcond_i32: > + =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_out_setcond_i32(s, args[3], args[0], arg= s[1], > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0args[2], const_args[2]); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0break; > + > =C2=A0#if TCG_TARGET_REG_BITS =3D=3D 32 > =C2=A0 =C2=A0 case INDEX_op_brcond2_i32: > =C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_out_brcond2_i32(s, args[4], args[0], args= [1], > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 args[2], const_args[2], > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 args[3], const_args[3], args[5]); > =C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > + =C2=A0 =C2=A0case INDEX_op_setcond2_i32: > + =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_out_setcond2_i32(s, args[5], args[0], ar= gs[1], args[2], > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 args[3], const_args[3], > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 args[4], const_args[4]); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0break; > =C2=A0 =C2=A0 case INDEX_op_add2_i32: > =C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_out_arithc(s, args[0], args[2], args[4], = const_args[4], > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0ARITH_ADDCC); > @@ -1257,6 +1375,11 @@ static inline void tcg_out_op(TCGContext *s, int o= pc, const TCGArg *args, > =C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_out_brcond_i64(s, args[2], args[0], args[= 1], const_args[1], > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0args[3]); > =C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > + =C2=A0 =C2=A0case INDEX_op_setcond_i64: > + =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_out_setcond_i64(s, args[3], args[0], arg= s[1], > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0args[2], const_args[2]); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0break; > + > =C2=A0 =C2=A0 case INDEX_op_qemu_ld64: > =C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_out_qemu_ld(s, args, 3); > =C2=A0 =C2=A0 =C2=A0 =C2=A0 break; > @@ -1309,8 +1432,11 @@ static const TCGTargetOpDef sparc_op_defs[] =3D { > =C2=A0 =C2=A0 { INDEX_op_sar_i32, { "r", "r", "rJ" } }, > > =C2=A0 =C2=A0 { INDEX_op_brcond_i32, { "r", "rJ" } }, > + =C2=A0 =C2=A0{ INDEX_op_setcond_i32, { "r", "r", "rJ" } }, > + > =C2=A0#if TCG_TARGET_REG_BITS =3D=3D 32 > =C2=A0 =C2=A0 { INDEX_op_brcond2_i32, { "r", "r", "rJ", "rJ" } }, > + =C2=A0 =C2=A0{ INDEX_op_setcond2_i32, { "r", "r", "r", "rJ", "rJ" } }, > =C2=A0 =C2=A0 { INDEX_op_add2_i32, { "r", "r", "r", "r", "rJ", "rJ" } }, > =C2=A0 =C2=A0 { INDEX_op_sub2_i32, { "r", "r", "r", "r", "rJ", "rJ" } }, > =C2=A0 =C2=A0 { INDEX_op_mulu2_i32, { "r", "r", "r", "rJ" } }, > @@ -1362,6 +1488,7 @@ static const TCGTargetOpDef sparc_op_defs[] =3D { > =C2=A0 =C2=A0 { INDEX_op_ext32u_i64, { "r", "ri" } }, > > =C2=A0 =C2=A0 { INDEX_op_brcond_i64, { "r", "rJ" } }, > + =C2=A0 =C2=A0{ INDEX_op_setcond_i64, { "r", "r", "rJ" } }, > =C2=A0#endif > =C2=A0 =C2=A0 { -1 }, > =C2=A0}; >