From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NhojY-0006vd-IH for qemu-devel@nongnu.org; Wed, 17 Feb 2010 13:34:48 -0500 Received: from [199.232.76.173] (port=45177 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NhojX-0006vR-8H for qemu-devel@nongnu.org; Wed, 17 Feb 2010 13:34:47 -0500 Received: from Debian-exim by monty-python.gnu.org with spam-scanned (Exim 4.60) (envelope-from ) id 1NhojW-0003Zn-Dm for qemu-devel@nongnu.org; Wed, 17 Feb 2010 13:34:47 -0500 Received: from mail-pz0-f187.google.com ([209.85.222.187]:41916) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NhojW-0003Zh-2w for qemu-devel@nongnu.org; Wed, 17 Feb 2010 13:34:46 -0500 Received: by pzk17 with SMTP id 17so6603369pzk.4 for ; Wed, 17 Feb 2010 10:34:45 -0800 (PST) MIME-Version: 1.0 In-Reply-To: References: From: Blue Swirl Date: Wed, 17 Feb 2010 20:34:25 +0200 Message-ID: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] Re: [PATCH 3/6] tcg: Optional target implementation of ANDC. List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: qemu-devel@nongnu.org On Wed, Feb 17, 2010 at 12:10 AM, Richard Henderson wrote= : > Previously ANDC was always implemented by tcg-op.h with > an explicit NOT opcode. =C2=A0Allow a target implementation. I think the convention is to add commented out #defines or #undefs for all targets, like sparc in bswap case: //#define TCG_TARGET_HAS_bswap32_i32 //#define TCG_TARGET_HAS_bswap64_i64 or mips: #undef TCG_TARGET_HAS_bswap32_i32 #undef TCG_TARGET_HAS_bswap16_i32 Then as each target maintainer decides whether it's a good idea to implement the optional feature, the #undef can be changed to #define as needed. The same also applies to ORC patch (#4). > > Signed-off-by: Richard Henderson > --- > =C2=A0tcg/tcg-op.h =C2=A0| =C2=A0 11 +++++++++++ > =C2=A0tcg/tcg-opc.h | =C2=A0 =C2=A06 ++++++ > =C2=A02 files changed, 17 insertions(+), 0 deletions(-) > > diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h > index 13eaa5a..447878d 100644 > --- a/tcg/tcg-op.h > +++ b/tcg/tcg-op.h > @@ -1650,20 +1650,31 @@ static inline void tcg_gen_concat32_i64(TCGv_i64 = dest, TCGv_i64 low, TCGv_i64 hi > > =C2=A0static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TC= Gv_i32 arg2) > =C2=A0{ > +#ifdef TCG_TARGET_HAS_andc_i32 > + =C2=A0 =C2=A0tcg_gen_op3_i32(INDEX_op_andc_i32, ret, arg1, arg2); > +#else > =C2=A0 =C2=A0 TCGv_i32 t0; > =C2=A0 =C2=A0 t0 =3D tcg_temp_new_i32(); > =C2=A0 =C2=A0 tcg_gen_not_i32(t0, arg2); > =C2=A0 =C2=A0 tcg_gen_and_i32(ret, arg1, t0); > =C2=A0 =C2=A0 tcg_temp_free_i32(t0); > +#endif > =C2=A0} > > =C2=A0static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TC= Gv_i64 arg2) > =C2=A0{ > +#ifdef TCG_TARGET_HAS_andc_i64 > + =C2=A0 =C2=A0tcg_gen_op3_i64(INDEX_op_andc_i64, ret, arg1, arg2); > +#elif defined(TCG_TARGET_HAS_andc_i32) && TCG_TARGET_REG_BITS =3D=3D 32 > + =C2=A0 =C2=A0tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(a= rg2)); > + =C2=A0 =C2=A0tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIG= H(arg2)); > +#else > =C2=A0 =C2=A0 TCGv_i64 t0; > =C2=A0 =C2=A0 t0 =3D tcg_temp_new_i64(); > =C2=A0 =C2=A0 tcg_gen_not_i64(t0, arg2); > =C2=A0 =C2=A0 tcg_gen_and_i64(ret, arg1, t0); > =C2=A0 =C2=A0 tcg_temp_free_i64(t0); > +#endif > =C2=A0} > > =C2=A0static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCG= v_i32 arg2) > diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h > index 89db3b4..6d855a7 100644 > --- a/tcg/tcg-opc.h > +++ b/tcg/tcg-opc.h > @@ -109,6 +109,9 @@ DEF2(not_i32, 1, 1, 0, 0) > =C2=A0#ifdef TCG_TARGET_HAS_neg_i32 > =C2=A0DEF2(neg_i32, 1, 1, 0, 0) > =C2=A0#endif > +#ifdef TCG_TARGET_HAS_andc_i32 > +DEF2(andc_i32, 1, 2, 0, 0) > +#endif > > =C2=A0#if TCG_TARGET_REG_BITS =3D=3D 64 > =C2=A0DEF2(mov_i64, 1, 1, 0, 0) > @@ -185,6 +188,9 @@ DEF2(not_i64, 1, 1, 0, 0) > =C2=A0#ifdef TCG_TARGET_HAS_neg_i64 > =C2=A0DEF2(neg_i64, 1, 1, 0, 0) > =C2=A0#endif > +#ifdef TCG_TARGET_HAS_andc_i64 > +DEF2(andc_i64, 1, 2, 0, 0) > +#endif > =C2=A0#endif > > =C2=A0/* QEMU specific */ > -- > 1.6.2.5 > >