[Qemu-devel] How to get 64-bit MMIO?

[Qemu-devel] How to get 64-bit MMIO?

[Dmitry Antipov]

Hello all,

is there any support for 64-bit MMIO?

I'm trying to emulate 16750-like UART by adopting current 16550A emulation.
The problem is that my (MIPS) hardware is 64-bit, and native software
issues 64-bit load/stores (LD/SD) to talk with all hardware registers,
which are all 64-bit too (for UART case, only 8 lower bits are used, BTW).
As I can see, qemu splits 64-bit access into two 32-bit back-to-back ones,
but this gives catastrophic results if host and guest has different
byte order - i.e. write 0x0000000000000001 to 0x100 gives write 0x00000000
to 0x100 and 0x10000000 to 0x104 because 64-bit quantities are swapped within
32-bit halves.

Dmitry

Re: [Qemu-devel] How to get 64-bit MMIO?

[Blue Swirl]

On Thu, Feb 18, 2010 at 4:41 PM, Dmitry Antipov <antipov@mvista.com> wrote:
> Hello all,
>
> is there any support for 64-bit MMIO?

No, though there has been some discussion about it before which you
can find in the archives. 64 bit MMIO would be useful for Sparc32,
Sparc64 and Alpha.

> I'm trying to emulate 16750-like UART by adopting current 16550A emulation.
> The problem is that my (MIPS) hardware is 64-bit, and native software
> issues 64-bit load/stores (LD/SD) to talk with all hardware registers,
> which are all 64-bit too (for UART case, only 8 lower bits are used, BTW).
> As I can see, qemu splits 64-bit access into two 32-bit back-to-back ones,
> but this gives catastrophic results if host and guest has different
> byte order - i.e. write 0x0000000000000001 to 0x100 gives write 0x00000000
> to 0x100 and 0x10000000 to 0x104 because 64-bit quantities are swapped
> within
> 32-bit halves.

The numbers don't look correct. Anyway, I'd suspect the device should
do some byte swapping. Without code it's hard to tell.