From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NinFn-0000sn-Mu for qemu-devel@nongnu.org; Sat, 20 Feb 2010 06:12:07 -0500 Received: from [199.232.76.173] (port=36410 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NinFl-0000sV-V0 for qemu-devel@nongnu.org; Sat, 20 Feb 2010 06:12:06 -0500 Received: from Debian-exim by monty-python.gnu.org with spam-scanned (Exim 4.60) (envelope-from ) id 1NinFj-0001KG-4m for qemu-devel@nongnu.org; Sat, 20 Feb 2010 06:12:05 -0500 Received: from mail-pw0-f45.google.com ([209.85.160.45]:63311) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NinFi-0001K0-QW for qemu-devel@nongnu.org; Sat, 20 Feb 2010 06:12:03 -0500 Received: by pwi4 with SMTP id 4so888279pwi.4 for ; Sat, 20 Feb 2010 03:12:01 -0800 (PST) MIME-Version: 1.0 In-Reply-To: References: Date: Sat, 20 Feb 2010 13:12:01 +0200 Message-ID: Subject: Re: [Qemu-devel] [PATCH v2] target-sparc: fix --enable-debug build From: Blue Swirl Content-Type: text/plain; charset=UTF-8 List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Jay Foad Cc: qemu-devel@nongnu.org Thanks, applied. On 2/20/10, Jay Foad wrote: > Use 32-bit arithmetic for the address offset calculation to fix a > build failure on 32-bit hosts. > > Signed-off-by: Jay Foad > --- > target-sparc/translate.c | 22 +++++++++++----------- > 1 files changed, 11 insertions(+), 11 deletions(-) > > diff --git a/target-sparc/translate.c b/target-sparc/translate.c > index 7e9f0cf..b7d2a32 100644 > --- a/target-sparc/translate.c > +++ b/target-sparc/translate.c > @@ -1663,27 +1663,27 @@ static inline TCGv get_src2(unsigned int insn, TCGv def) > #ifdef TARGET_SPARC64 > static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, > TCGv_ptr cpu_env) > { > - TCGv r_tl = tcg_temp_new(); > + TCGv_i32 r_tl = tcg_temp_new_i32(); > > /* load env->tl into r_tl */ > - { > - TCGv_i32 r_tl_tmp = tcg_temp_new_i32(); > - tcg_gen_ld_i32(r_tl_tmp, cpu_env, offsetof(CPUSPARCState, tl)); > - tcg_gen_ext_i32_tl(r_tl, r_tl_tmp); > - tcg_temp_free_i32(r_tl_tmp); > - } > + tcg_gen_ld_i32(r_tl, cpu_env, offsetof(CPUSPARCState, tl)); > > /* tl = [0 ... MAXTL_MASK] where MAXTL_MASK must be power of 2 */ > - tcg_gen_andi_tl(r_tl, r_tl, MAXTL_MASK); > + tcg_gen_andi_i32(r_tl, r_tl, MAXTL_MASK); > > /* calculate offset to current trap state from env->ts, reuse r_tl */ > - tcg_gen_muli_tl(r_tl, r_tl, sizeof (trap_state)); > + tcg_gen_muli_i32(r_tl, r_tl, sizeof (trap_state)); > tcg_gen_addi_ptr(r_tsptr, cpu_env, offsetof(CPUState, ts)); > > /* tsptr = env->ts[env->tl & MAXTL_MASK] */ > - tcg_gen_add_ptr(r_tsptr, r_tsptr, r_tl); > + { > + TCGv_ptr r_tl_tmp = tcg_temp_new_ptr(); > + tcg_gen_ext_i32_ptr(r_tl_tmp, r_tl); > + tcg_gen_add_ptr(r_tsptr, r_tsptr, r_tl_tmp); > + tcg_temp_free_i32(r_tl_tmp); > + } > > - tcg_temp_free(r_tl); > + tcg_temp_free_i32(r_tl); > } > #endif > > >