From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: "Zheyu Ma" <zheyuma97@gmail.com>,
"Cédric Le Goater" <clg@kaod.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Joel Stanley" <joel@jms.id.au>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH v3] hw/gpio/aspeed: Add reg_table_size to AspeedGPIOClass
Date: Thu, 20 Jun 2024 13:09:05 +0200 [thread overview]
Message-ID: <f446fdbf-90f2-4d07-8f1f-06b697ec8c01@linaro.org> (raw)
In-Reply-To: <20240619183638.4073070-1-zheyuma97@gmail.com>
Hi,
On 19/6/24 20:36, Zheyu Ma wrote:
> ASan detected a global-buffer-overflow error in the aspeed_gpio_read()
> function. This issue occurred when reading beyond the bounds of the
> reg_table.
>
> To enhance the safety and maintainability of the Aspeed GPIO code, this commit
> introduces a reg_table_size member to the AspeedGPIOClass structure. This
> change ensures that the size of the GPIO register table is explicitly tracked
> and initialized, reducing the risk of errors if new register tables are
> introduced in the future.
>
> Reproducer:
> cat << EOF | qemu-system-aarch64 -display none \
> -machine accel=qtest, -m 512M -machine ast1030-evb -qtest stdio
> readq 0x7e780272
> EOF
>
> ASAN log indicating the issue:
> ==2602930==ERROR: AddressSanitizer: global-buffer-overflow on address 0x55a5da29e128 at pc 0x55a5d700dc62 bp 0x7fff096c4e90 sp 0x7fff096c4e88
> READ of size 2 at 0x55a5da29e128 thread T0
> #0 0x55a5d700dc61 in aspeed_gpio_read hw/gpio/aspeed_gpio.c:564:14
> #1 0x55a5d933f3ab in memory_region_read_accessor system/memory.c:445:11
> #2 0x55a5d92fba40 in access_with_adjusted_size system/memory.c:573:18
> #3 0x55a5d92f842c in memory_region_dispatch_read1 system/memory.c:1426:16
> #4 0x55a5d92f7b68 in memory_region_dispatch_read system/memory.c:1459:9
> #5 0x55a5d9376ad1 in flatview_read_continue_step system/physmem.c:2836:18
> #6 0x55a5d9376399 in flatview_read_continue system/physmem.c:2877:19
> #7 0x55a5d93775b8 in flatview_read system/physmem.c:2907:12
>
> Signed-off-by: Zheyu Ma <zheyuma97@gmail.com>
> ---
> Changes in v3:
> - Add the reproducer
>
> Changes in v2:
> - Introduce the reg_table_size to AspeedGPIOClass
> ---
> hw/gpio/aspeed_gpio.c | 17 +++++++++++++++++
> include/hw/gpio/aspeed_gpio.h | 1 +
> 2 files changed, 18 insertions(+)
> static const TypeInfo aspeed_gpio_info = {
> diff --git a/include/hw/gpio/aspeed_gpio.h b/include/hw/gpio/aspeed_gpio.h
> index 904eecf62c..e66036ac39 100644
> --- a/include/hw/gpio/aspeed_gpio.h
> +++ b/include/hw/gpio/aspeed_gpio.h
> @@ -75,6 +75,7 @@ struct AspeedGPIOClass {
> uint32_t nr_gpio_pins;
> uint32_t nr_gpio_sets;
> const AspeedGPIOReg *reg_table;
> + uint32_t reg_table_size;
> };
- "reg_table_size" is a number of registers, using s/size/count/ might
be clearer.
- No point in specifying 32-bit, "unsigned" is sufficient.
(Cédric, if you agree, you might update your tree).
Unrelated to this patch but figured out while reviewing, in
aspeed_gpio_read/write 'idx' is
- pointlessly assigned to -1
- of type 'uint64_t', also pointless, 'unsigned' is clearer.
Regards,
Phil.
next prev parent reply other threads:[~2024-06-20 11:10 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-19 18:36 [PATCH v3] hw/gpio/aspeed: Add reg_table_size to AspeedGPIOClass Zheyu Ma
2024-06-19 23:48 ` Andrew Jeffery
2024-06-20 5:44 ` Cédric Le Goater
2024-06-20 11:09 ` Philippe Mathieu-Daudé [this message]
2024-06-20 12:35 ` Cédric Le Goater
2024-06-20 14:03 ` Zheyu Ma
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