From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: Re: [PATCH 02/22] target/riscv: introduce RISCVCPUDef
Date: Thu, 6 Feb 2025 13:16:26 -0800 [thread overview]
Message-ID: <f4ec871d-e759-44bc-a10b-872322330a3f@linaro.org> (raw)
In-Reply-To: <20250206182711.2420505-3-pbonzini@redhat.com>
On 2/6/25 10:26, Paolo Bonzini wrote:
> Start putting all the CPU definitions in a struct. Later this will replace
> instance_init functions with declarative code, for now just remove the
> ugly cast of class_data.
...
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index ed9da692030..29cfae38b75 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2955,7 +2955,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
> {
> RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
>
> - mcc->misa_mxl_max = (uint32_t)(uintptr_t)data;
> + mcc->misa_mxl_max = ((RISCVCPUDef *)data)->misa_mxl_max;
> riscv_cpu_validate_misa_mxl(mcc);
> }
>
> @@ -3051,40 +3051,48 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
> }
> #endif
>
> -#define DEFINE_DYNAMIC_CPU(type_name, misa_mxl_max, initfn) \
> +#define DEFINE_DYNAMIC_CPU(type_name, misa_mxl_max_, initfn) \
> { \
> .name = (type_name), \
> .parent = TYPE_RISCV_DYNAMIC_CPU, \
> .instance_init = (initfn), \
> .class_init = riscv_cpu_class_init, \
> - .class_data = (void *)(misa_mxl_max) \
> + .class_data = &((RISCVCPUDef) { \
> + .misa_mxl_max = (misa_mxl_max_), \
> + }), \
Drop the unnecessary ().
It would be nice if this were const, i.e.
.class_data = (void *) &(const RISCVCPUDef){
...
},
This will in fact create an anonymous object in .rodata.
We have other uses that do the extra casting away const,
e.g. armsse_variants in hw/arm/armsse.c. Although I suspect
*all* usage of .class_init can and should be with const data.
An unrelated cleanup, to be sure.
r~
next prev parent reply other threads:[~2025-02-06 21:17 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-06 18:26 [PATCH 00/22] target/riscv: declarative CPU definitions Paolo Bonzini
2025-02-06 18:26 ` [PATCH 01/22] target/riscv: remove unused macro DEFINE_CPU Paolo Bonzini
2025-02-10 0:44 ` Alistair Francis
2025-02-06 18:26 ` [PATCH 02/22] target/riscv: introduce RISCVCPUDef Paolo Bonzini
2025-02-06 21:16 ` Richard Henderson [this message]
2025-02-09 18:44 ` Philippe Mathieu-Daudé
2025-02-09 18:53 ` Philippe Mathieu-Daudé
2025-02-09 22:20 ` Philippe Mathieu-Daudé
2025-02-09 22:32 ` Philippe Mathieu-Daudé
2025-02-06 18:26 ` [PATCH 03/22] target/riscv: store RISCVCPUDef struct directly in the class Paolo Bonzini
2025-02-18 0:02 ` Alistair Francis
2025-02-06 18:26 ` [PATCH 04/22] target/riscv: merge riscv_cpu_class_init with the class_base function Paolo Bonzini
2025-02-18 0:05 ` Alistair Francis
2025-02-06 18:26 ` [PATCH 05/22] target/riscv: move RISCVCPUConfig fields to a header file Paolo Bonzini
2025-02-18 0:06 ` Alistair Francis
2025-02-06 18:26 ` [PATCH 06/22] target/riscv: add more RISCVCPUDef fields Paolo Bonzini
2025-02-18 0:23 ` Alistair Francis
2025-02-18 9:30 ` Paolo Bonzini
2025-02-06 18:26 ` [PATCH 07/22] target/riscv: convert abstract CPU classes to RISCVCPUDef Paolo Bonzini
2025-02-06 18:26 ` [PATCH 08/22] target/riscv: convert profile CPU models " Paolo Bonzini
2025-02-06 18:26 ` [PATCH 09/22] target/riscv: convert bare " Paolo Bonzini
2025-02-06 18:26 ` [PATCH 10/22] target/riscv: move 128-bit check to TCG realize Paolo Bonzini
2025-02-06 18:26 ` [PATCH 11/22] target/riscv: convert dynamic CPU models to RISCVCPUDef Paolo Bonzini
2025-02-06 18:27 ` [PATCH 12/22] target/riscv: convert SiFive E " Paolo Bonzini
2025-02-06 18:27 ` [PATCH 13/22] target/riscv: convert ibex " Paolo Bonzini
2025-02-06 18:27 ` [PATCH 14/22] target/riscv: convert SiFive U " Paolo Bonzini
2025-02-06 18:27 ` [PATCH 15/22] target/riscv: th: make CSR insertion test a bit more intuitive Paolo Bonzini
2025-02-06 18:27 ` [PATCH 16/22] target/riscv: generalize custom CSR functionality Paolo Bonzini
2025-02-06 18:27 ` [PATCH 17/22] target/riscv: convert TT C906 to RISCVCPUDef Paolo Bonzini
2025-02-06 18:27 ` [PATCH 18/22] target/riscv: convert TT Ascalon " Paolo Bonzini
2025-02-06 18:27 ` [PATCH 19/22] target/riscv: convert Ventana V1 " Paolo Bonzini
2025-02-06 18:27 ` [PATCH 20/22] target/riscv: convert Xiangshan Nanhu " Paolo Bonzini
2025-02-06 18:27 ` [PATCH 21/22] target/riscv: remove .instance_post_init Paolo Bonzini
2025-02-06 18:27 ` [PATCH 22/22] target/riscv: move SATP modes out of CPUConfig Paolo Bonzini
2025-02-18 0:25 ` [PATCH 00/22] target/riscv: declarative CPU definitions Alistair Francis
2025-02-18 8:27 ` Paolo Bonzini
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