From: Richard Henderson <richard.henderson@linaro.org>
To: "Alex Bennée" <alex.bennee@linaro.org>, qemu-arm@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v2 23/32] arm/helper.c: re-factor recpe and add recepe_f16
Date: Fri, 9 Feb 2018 09:54:58 -0800 [thread overview]
Message-ID: <f5093f9e-23b3-3d04-7a5b-038619d89d63@linaro.org> (raw)
In-Reply-To: <20180208173157.24705-24-alex.bennee@linaro.org>
On 02/08/2018 09:31 AM, Alex Bennée wrote:
> +float16 HELPER(recpe_f16)(float16 input, void *fpstp)
> +{
> + float_status *fpst = fpstp;
> + float16 f16 = float16_squash_input_denormal(input, fpst);
> + uint32_t f16_val = float16_val(f16);
> + uint32_t f16_sign = float16_is_neg(f16);
> + int f16_exp = extract32(f16_val, 10, 5);
> + uint32_t f16_frac = extract32(f16_val, 0, 10);
> + uint64_t f64_frac;
> +
> + if (float16_is_any_nan(f16)) {
> + float16 nan = f16;
> + if (float16_is_signaling_nan(f16, fpst)) {
> + float_raise(float_flag_invalid, fpst);
> + nan = float16_maybe_silence_nan(f16, fpst);
> + }
> + if (fpst->default_nan_mode) {
> + nan = float16_default_nan(fpst);
> + }
> + return nan;
> + } else if (float16_is_infinity(f16)) {
> + return float16_set_sign(float16_zero, float16_is_neg(f16));
> + } else if (float16_is_zero(f16)) {
> + float_raise(float_flag_divbyzero, fpst);
> + return float16_set_sign(float16_infinity, float16_is_neg(f16));
> + } else if (float16_abs(f16) < (1 << 8)) {
> + /* Abs(value) < 2.0^-14 */
The pseudocode I'm looking at says 2.0^-16. But I think the code is right --
this is checking for two zero bits at the top of a denormal, so that is
2.0^(-14-2).
> + float_raise(float_flag_overflow | float_flag_inexact, fpst);
> + if (round_to_inf(fpst, f16_sign)) {
> + return float16_set_sign(float16_infinity, f16_sign);
> + } else {
> + return float16_set_sign(float16_maxnorm, f16_sign);
> + }
> + /* FP16 has it's own flag FZ16 flag which is in a separate fpst*/
> + } else if (f16_exp >= 14 && fpst->flush_to_zero) {
(1) The comment is confusing.
(a) It's placement within the previous IF is not helpful,
(b) Why mention the separate fpst, begging the question of
where it is? We're using it, of course, so...
(2) The exponent is still biased, so this isn't 2.0^14 you're testing.
> } else if (f32_exp >= 253 && fpst->flush_to_zero) {
E.g. the single-precision version tests (2^)126 + (bias)127.
r~
next prev parent reply other threads:[~2018-02-09 17:55 UTC|newest]
Thread overview: 79+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-08 17:31 [Qemu-devel] [PATCH v2 00/32] Add ARMv8.2 half-precision functions Alex Bennée
2018-02-08 17:31 ` [Qemu-devel] [PATCH v2 01/32] include/exec/helper-head.h: support f16 in helper calls Alex Bennée
2018-02-08 17:31 ` [Qemu-devel] [PATCH v2 02/32] target/arm/cpu64: introduce ARM_V8_FP16 feature bit Alex Bennée
2018-02-08 17:31 ` [Qemu-devel] [PATCH v2 03/32] target/arm/cpu64: allow fp16 to be disabled Alex Bennée
2018-02-08 20:36 ` Richard Henderson
2018-02-13 14:26 ` Peter Maydell
2018-02-21 16:35 ` Alex Bennée
2018-02-21 18:16 ` Richard Henderson
2018-02-08 17:31 ` [Qemu-devel] [PATCH v2 04/32] target/arm/cpu.h: update comment for half-precision values Alex Bennée
2018-02-08 17:31 ` [Qemu-devel] [PATCH v2 05/32] target/arm/cpu.h: add additional float_status flags Alex Bennée
2018-02-08 20:42 ` Richard Henderson
2018-02-08 17:31 ` [Qemu-devel] [PATCH v2 06/32] target/arm/helper: pass explicit fpst to set_rmode Alex Bennée
2018-02-08 20:43 ` Richard Henderson
2018-02-08 17:31 ` [Qemu-devel] [PATCH v2 07/32] arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV) Alex Bennée
2018-02-08 20:46 ` Richard Henderson
2018-02-08 20:49 ` Richard Henderson
2018-02-08 17:31 ` [Qemu-devel] [PATCH v2 08/32] arm/translate-a64: handle_3same_64 comment fix Alex Bennée
2018-02-08 20:46 ` Richard Henderson
2018-02-08 17:31 ` [Qemu-devel] [PATCH v2 09/32] arm/translate-a64: initial decode for simd_three_reg_same_fp16 Alex Bennée
2018-02-08 20:48 ` Richard Henderson
2018-02-08 17:31 ` [Qemu-devel] [PATCH v2 10/32] arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16 Alex Bennée
2018-02-08 20:49 ` Richard Henderson
2018-02-08 17:31 ` [Qemu-devel] [PATCH v2 11/32] arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] " Alex Bennée
2018-02-08 20:54 ` Richard Henderson
2018-02-23 11:59 ` Alex Bennée
2018-02-23 22:10 ` Richard Henderson
2018-02-08 17:31 ` [Qemu-devel] [PATCH v2 12/32] arm/translate-a64: add FP16 FMULA/X/S " Alex Bennée
2018-02-08 20:56 ` Richard Henderson
2018-02-08 17:31 ` [Qemu-devel] [PATCH v2 13/32] arm/translate-a64: add FP16 FR[ECP/SQRT]S " Alex Bennée
2018-02-08 20:59 ` Richard Henderson
2018-02-08 17:31 ` [Qemu-devel] [PATCH v2 14/32] arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16 Alex Bennée
2018-02-08 21:30 ` Richard Henderson
2018-02-08 17:31 ` [Qemu-devel] [PATCH v2 15/32] arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed Alex Bennée
2018-02-08 21:49 ` Richard Henderson
2018-02-08 17:31 ` [Qemu-devel] [PATCH v2 16/32] arm/translate-a64: add FP16 x2 ops for simd_indexed Alex Bennée
2018-02-08 22:10 ` Richard Henderson
2018-02-08 17:31 ` [Qemu-devel] [PATCH v2 17/32] arm/translate-a64: initial decode for simd_two_reg_misc_fp16 Alex Bennée
2018-02-08 22:15 ` Richard Henderson
2018-02-08 17:31 ` [Qemu-devel] [PATCH v2 18/32] arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16 Alex Bennée
2018-02-08 22:32 ` Richard Henderson
2018-02-08 17:31 ` [Qemu-devel] [PATCH v2 19/32] arm/translate-a64: add FCVTxx " Alex Bennée
2018-02-08 22:35 ` Richard Henderson
2018-02-08 17:31 ` [Qemu-devel] [PATCH v2 20/32] arm/translate-a64: add FP16 FCMxx (zero) " Alex Bennée
2018-02-08 22:39 ` Richard Henderson
2018-02-22 17:23 ` Alex Bennée
2018-02-22 19:40 ` Richard Henderson
2018-02-23 10:23 ` Alex Bennée
2018-02-08 17:31 ` [Qemu-devel] [PATCH v2 21/32] arm/translate-a64: add FP16 SCVTF/UCVFT " Alex Bennée
2018-02-08 22:42 ` Richard Henderson
2018-02-08 17:31 ` [Qemu-devel] [PATCH v2 22/32] arm/translate-a64: add FP16 FNEG/FABS " Alex Bennée
2018-02-08 22:43 ` Richard Henderson
2018-02-08 17:31 ` [Qemu-devel] [PATCH v2 23/32] arm/helper.c: re-factor recpe and add recepe_f16 Alex Bennée
2018-02-09 17:54 ` Richard Henderson [this message]
2018-02-08 17:31 ` [Qemu-devel] [PATCH v2 24/32] arm/translate-a64: add FP16 FRECPE Alex Bennée
2018-02-09 17:57 ` Richard Henderson
2018-02-08 17:31 ` [Qemu-devel] [PATCH v2 25/32] arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16 Alex Bennée
2018-02-09 18:00 ` Richard Henderson
2018-02-08 17:31 ` [Qemu-devel] [PATCH v2 26/32] arm/translate-a64: add FP16 FSQRT " Alex Bennée
2018-02-09 18:01 ` Richard Henderson
2018-02-08 17:31 ` [Qemu-devel] [PATCH v2 27/32] arm/helper.c: re-factor rsqrte and add rsqrte_f16 Alex Bennée
2018-02-09 18:15 ` Richard Henderson
2018-02-08 17:31 ` [Qemu-devel] [PATCH v2 28/32] arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16 Alex Bennée
2018-02-09 18:15 ` Richard Henderson
2018-02-08 17:31 ` [Qemu-devel] [PATCH v2 29/32] arm/translate-a64: add FP16 FMOV to simd_mod_imm Alex Bennée
2018-02-09 18:23 ` Richard Henderson
2018-02-08 17:31 ` [Qemu-devel] [PATCH v2 30/32] arm/translate-a64: add all FP16 ops in simd_scalar_pairwise Alex Bennée
2018-02-09 18:27 ` Richard Henderson
2018-02-08 17:31 ` [Qemu-devel] [PATCH v2 31/32] arm/translate-a64: implement simd_scalar_three_reg_same_fp16 Alex Bennée
2018-02-09 18:34 ` Richard Henderson
2018-02-08 17:31 ` [Qemu-devel] [PATCH v2 32/32] arm/translate-a64: add all single op FP16 to handle_fp_1src_half Alex Bennée
2018-02-09 18:37 ` Richard Henderson
2018-02-23 9:45 ` Alex Bennée
2018-02-08 18:49 ` [Qemu-devel] [PATCH v2 00/32] Add ARMv8.2 half-precision functions no-reply
2018-02-08 18:56 ` no-reply
2018-02-08 19:04 ` no-reply
2018-02-08 19:11 ` no-reply
2018-02-08 19:17 ` no-reply
2018-02-08 21:33 ` no-reply
2018-02-13 14:27 ` [Qemu-devel] [Qemu-arm] " Peter Maydell
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