* [PATCH] accel/tcg: Name gen_goto_tb()'s TB slot index as @tb_slot_idx
@ 2025-10-10 3:17 Philippe Mathieu-Daudé
2025-10-15 16:52 ` Philippe Mathieu-Daudé
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-10 3:17 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson
tcg_gen_goto_tb() takes an unsigned index to the TB slot (0 or 1).
Declare the argument as unsigned and rename it as @tb_slot_idx
(which is more descriptive than @n) on all targets.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/alpha/translate.c | 8 ++++----
target/arm/tcg/translate-a64.c | 8 ++++----
target/arm/tcg/translate.c | 8 ++++----
target/avr/translate.c | 7 ++++---
target/hexagon/translate.c | 8 ++++----
target/loongarch/tcg/translate.c | 7 ++++---
target/microblaze/translate.c | 7 ++++---
target/mips/tcg/translate.c | 7 ++++---
target/ppc/translate.c | 7 ++++---
target/riscv/translate.c | 9 +++++----
target/rx/translate.c | 7 ++++---
target/sh4/translate.c | 7 ++++---
target/sparc/translate.c | 6 +++---
target/tricore/translate.c | 7 ++++---
14 files changed, 56 insertions(+), 47 deletions(-)
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index f11b382438c..a492520075e 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -436,18 +436,18 @@ static DisasJumpType gen_store_conditional(DisasContext *ctx, int ra, int rb,
return DISAS_NEXT;
}
-static void gen_goto_tb(DisasContext *ctx, int idx, int32_t disp)
+static void gen_goto_tb(DisasContext *ctx, unsigned tb_slot_idx, int32_t disp)
{
if (translator_use_goto_tb(&ctx->base, ctx->base.pc_next + disp)) {
/* With PCREL, PC must always be up-to-date. */
if (ctx->pcrel) {
gen_pc_disp(ctx, cpu_pc, disp);
- tcg_gen_goto_tb(idx);
+ tcg_gen_goto_tb(tb_slot_idx);
} else {
- tcg_gen_goto_tb(idx);
+ tcg_gen_goto_tb(tb_slot_idx);
gen_pc_disp(ctx, cpu_pc, disp);
}
- tcg_gen_exit_tb(ctx->base.tb, idx);
+ tcg_gen_exit_tb(ctx->base.tb, tb_slot_idx);
} else {
gen_pc_disp(ctx, cpu_pc, disp);
tcg_gen_lookup_and_goto_ptr();
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index a0e3300231f..20c2a5b4861 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -471,7 +471,7 @@ static inline bool use_goto_tb(DisasContext *s, uint64_t dest)
return translator_use_goto_tb(&s->base, dest);
}
-static void gen_goto_tb(DisasContext *s, int n, int64_t diff)
+static void gen_goto_tb(DisasContext *s, unsigned tb_slot_idx, int64_t diff)
{
if (use_goto_tb(s, s->pc_curr + diff)) {
/*
@@ -484,12 +484,12 @@ static void gen_goto_tb(DisasContext *s, int n, int64_t diff)
*/
if (tb_cflags(s->base.tb) & CF_PCREL) {
gen_a64_update_pc(s, diff);
- tcg_gen_goto_tb(n);
+ tcg_gen_goto_tb(tb_slot_idx);
} else {
- tcg_gen_goto_tb(n);
+ tcg_gen_goto_tb(tb_slot_idx);
gen_a64_update_pc(s, diff);
}
- tcg_gen_exit_tb(s->base.tb, n);
+ tcg_gen_exit_tb(s->base.tb, tb_slot_idx);
s->base.is_jmp = DISAS_NORETURN;
} else {
gen_a64_update_pc(s, diff);
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
index e62dcc5d85d..51654b0b91d 100644
--- a/target/arm/tcg/translate.c
+++ b/target/arm/tcg/translate.c
@@ -1259,7 +1259,7 @@ static void gen_goto_ptr(void)
* cpu_loop_exec. Any live exit_requests will be processed as we
* enter the next TB.
*/
-static void gen_goto_tb(DisasContext *s, int n, target_long diff)
+static void gen_goto_tb(DisasContext *s, unsigned tb_slot_idx, target_long diff)
{
if (translator_use_goto_tb(&s->base, s->pc_curr + diff)) {
/*
@@ -1272,12 +1272,12 @@ static void gen_goto_tb(DisasContext *s, int n, target_long diff)
*/
if (tb_cflags(s->base.tb) & CF_PCREL) {
gen_update_pc(s, diff);
- tcg_gen_goto_tb(n);
+ tcg_gen_goto_tb(tb_slot_idx);
} else {
- tcg_gen_goto_tb(n);
+ tcg_gen_goto_tb(tb_slot_idx);
gen_update_pc(s, diff);
}
- tcg_gen_exit_tb(s->base.tb, n);
+ tcg_gen_exit_tb(s->base.tb, tb_slot_idx);
} else {
gen_update_pc(s, diff);
gen_goto_ptr();
diff --git a/target/avr/translate.c b/target/avr/translate.c
index 804b0b21dbd..ef6f655a458 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@ -981,14 +981,15 @@ static void gen_pop_ret(DisasContext *ctx, TCGv ret)
}
}
-static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
+static void gen_goto_tb(DisasContext *ctx, unsigned tb_slot_idx,
+ target_ulong dest)
{
const TranslationBlock *tb = ctx->base.tb;
if (translator_use_goto_tb(&ctx->base, dest)) {
- tcg_gen_goto_tb(n);
+ tcg_gen_goto_tb(tb_slot_idx);
tcg_gen_movi_i32(cpu_pc, dest);
- tcg_gen_exit_tb(tb, n);
+ tcg_gen_exit_tb(tb, tb_slot_idx);
} else {
tcg_gen_movi_i32(cpu_pc, dest);
tcg_gen_lookup_and_goto_ptr();
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index 02fd40c160f..50766eafe27 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -133,15 +133,15 @@ static bool use_goto_tb(DisasContext *ctx, target_ulong dest)
return translator_use_goto_tb(&ctx->base, dest);
}
-static void gen_goto_tb(DisasContext *ctx, int idx, target_ulong dest, bool
- move_to_pc)
+static void gen_goto_tb(DisasContext *ctx, unsigned tb_slot_idx,
+ target_ulong dest, bool move_to_pc)
{
if (use_goto_tb(ctx, dest)) {
- tcg_gen_goto_tb(idx);
+ tcg_gen_goto_tb(tb_slot_idx);
if (move_to_pc) {
tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], dest);
}
- tcg_gen_exit_tb(ctx->base.tb, idx);
+ tcg_gen_exit_tb(ctx->base.tb, tb_slot_idx);
} else {
if (move_to_pc) {
tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], dest);
diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/translate.c
index 53a0b4c3ce9..57c3b8c4bb2 100644
--- a/target/loongarch/tcg/translate.c
+++ b/target/loongarch/tcg/translate.c
@@ -99,16 +99,17 @@ void generate_exception(DisasContext *ctx, int excp)
ctx->base.is_jmp = DISAS_NORETURN;
}
-static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
+static void gen_goto_tb(DisasContext *ctx, unsigned tb_slot_idx,
+ target_ulong dest)
{
if (ctx->va32) {
dest = (uint32_t) dest;
}
if (translator_use_goto_tb(&ctx->base, dest)) {
- tcg_gen_goto_tb(n);
+ tcg_gen_goto_tb(tb_slot_idx);
tcg_gen_movi_tl(cpu_pc, dest);
- tcg_gen_exit_tb(ctx->base.tb, n);
+ tcg_gen_exit_tb(ctx->base.tb, tb_slot_idx);
} else {
tcg_gen_movi_tl(cpu_pc, dest);
tcg_gen_lookup_and_goto_ptr();
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 5098a1db4dc..3dd74b021e8 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -116,12 +116,13 @@ static void gen_raise_hw_excp(DisasContext *dc, uint32_t esr_ec)
gen_raise_exception_sync(dc, EXCP_HW_EXCP);
}
-static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
+static void gen_goto_tb(DisasContext *dc, unsigned tb_slot_idx,
+ target_ulong dest)
{
if (translator_use_goto_tb(&dc->base, dest)) {
- tcg_gen_goto_tb(n);
+ tcg_gen_goto_tb(tb_slot_idx);
tcg_gen_movi_i32(cpu_pc, dest);
- tcg_gen_exit_tb(dc->base.tb, n);
+ tcg_gen_exit_tb(dc->base.tb, tb_slot_idx);
} else {
tcg_gen_movi_i32(cpu_pc, dest);
tcg_gen_lookup_and_goto_ptr();
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index d91d6efe02c..54849e9ff1a 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -4362,12 +4362,13 @@ static void gen_trap(DisasContext *ctx, uint32_t opc,
}
}
-static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
+static void gen_goto_tb(DisasContext *ctx, unsigned tb_slot_idx,
+ target_ulong dest)
{
if (translator_use_goto_tb(&ctx->base, dest)) {
- tcg_gen_goto_tb(n);
+ tcg_gen_goto_tb(tb_slot_idx);
gen_save_pc(dest);
- tcg_gen_exit_tb(ctx->base.tb, n);
+ tcg_gen_exit_tb(ctx->base.tb, tb_slot_idx);
} else {
gen_save_pc(dest);
tcg_gen_lookup_and_goto_ptr();
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index d422789a1d0..17e6d07c8c2 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3668,16 +3668,17 @@ static void gen_lookup_and_goto_ptr(DisasContext *ctx)
}
/*** Branch ***/
-static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
+static void gen_goto_tb(DisasContext *ctx, unsigned tb_slot_idx,
+ target_ulong dest)
{
if (NARROW_MODE(ctx)) {
dest = (uint32_t) dest;
}
if (use_goto_tb(ctx, dest)) {
pmu_count_insns(ctx);
- tcg_gen_goto_tb(n);
+ tcg_gen_goto_tb(tb_slot_idx);
tcg_gen_movi_tl(cpu_nip, dest & ~3);
- tcg_gen_exit_tb(ctx->base.tb, n);
+ tcg_gen_exit_tb(ctx->base.tb, tb_slot_idx);
} else {
tcg_gen_movi_tl(cpu_nip, dest & ~3);
gen_lookup_and_goto_ptr(ctx);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 6fc06c71f51..9a53aecbfe9 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -286,7 +286,8 @@ static void exit_tb(DisasContext *ctx)
tcg_gen_exit_tb(NULL, 0);
}
-static void gen_goto_tb(DisasContext *ctx, int n, target_long diff)
+static void gen_goto_tb(DisasContext *ctx, unsigned tb_slot_idx,
+ target_long diff)
{
target_ulong dest = ctx->base.pc_next + diff;
@@ -305,12 +306,12 @@ static void gen_goto_tb(DisasContext *ctx, int n, target_long diff)
*/
if (tb_cflags(ctx->base.tb) & CF_PCREL) {
gen_update_pc(ctx, diff);
- tcg_gen_goto_tb(n);
+ tcg_gen_goto_tb(tb_slot_idx);
} else {
- tcg_gen_goto_tb(n);
+ tcg_gen_goto_tb(tb_slot_idx);
gen_update_pc(ctx, diff);
}
- tcg_gen_exit_tb(ctx->base.tb, n);
+ tcg_gen_exit_tb(ctx->base.tb, tb_slot_idx);
} else {
gen_update_pc(ctx, diff);
lookup_and_goto_ptr(ctx);
diff --git a/target/rx/translate.c b/target/rx/translate.c
index 19a9584a829..5fc589c706b 100644
--- a/target/rx/translate.c
+++ b/target/rx/translate.c
@@ -147,12 +147,13 @@ void rx_cpu_dump_state(CPUState *cs, FILE *f, int flags)
}
}
-static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
+static void gen_goto_tb(DisasContext *dc, unsigned tb_slot_idx,
+ target_ulong dest)
{
if (translator_use_goto_tb(&dc->base, dest)) {
- tcg_gen_goto_tb(n);
+ tcg_gen_goto_tb(tb_slot_idx);
tcg_gen_movi_i32(cpu_pc, dest);
- tcg_gen_exit_tb(dc->base.tb, n);
+ tcg_gen_exit_tb(dc->base.tb, tb_slot_idx);
} else {
tcg_gen_movi_i32(cpu_pc, dest);
tcg_gen_lookup_and_goto_ptr();
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 70fd13aa3f5..137b75a4fb2 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -231,12 +231,13 @@ static bool use_goto_tb(DisasContext *ctx, target_ulong dest)
return translator_use_goto_tb(&ctx->base, dest);
}
-static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
+static void gen_goto_tb(DisasContext *ctx, unsigned tb_slot_idx,
+ target_ulong dest)
{
if (use_goto_tb(ctx, dest)) {
- tcg_gen_goto_tb(n);
+ tcg_gen_goto_tb(tb_slot_idx);
tcg_gen_movi_i32(cpu_pc, dest);
- tcg_gen_exit_tb(ctx->base.tb, n);
+ tcg_gen_exit_tb(ctx->base.tb, tb_slot_idx);
} else {
tcg_gen_movi_i32(cpu_pc, dest);
if (use_exit_tb(ctx)) {
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 810e2491a61..d6b599b71fe 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -363,15 +363,15 @@ static bool use_goto_tb(DisasContext *s, target_ulong pc, target_ulong npc)
translator_use_goto_tb(&s->base, npc);
}
-static void gen_goto_tb(DisasContext *s, int tb_num,
+static void gen_goto_tb(DisasContext *s, unsigned tb_slot_idx,
target_ulong pc, target_ulong npc)
{
if (use_goto_tb(s, pc, npc)) {
/* jump to same page: we can use a direct jump */
- tcg_gen_goto_tb(tb_num);
+ tcg_gen_goto_tb(tb_slot_idx);
tcg_gen_movi_tl(cpu_pc, pc);
tcg_gen_movi_tl(cpu_npc, npc);
- tcg_gen_exit_tb(s->base.tb, tb_num);
+ tcg_gen_exit_tb(s->base.tb, tb_slot_idx);
} else {
/* jump to another page: we can use an indirect jump */
tcg_gen_movi_tl(cpu_pc, pc);
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 3d0e7a10bd8..7c6e3095971 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -2816,12 +2816,13 @@ static inline void gen_save_pc(target_ulong pc)
tcg_gen_movi_tl(cpu_PC, pc);
}
-static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
+static void gen_goto_tb(DisasContext *ctx, unsigned tb_slot_index,
+ target_ulong dest)
{
if (translator_use_goto_tb(&ctx->base, dest)) {
- tcg_gen_goto_tb(n);
+ tcg_gen_goto_tb(tb_slot_index);
gen_save_pc(dest);
- tcg_gen_exit_tb(ctx->base.tb, n);
+ tcg_gen_exit_tb(ctx->base.tb, tb_slot_index);
} else {
gen_save_pc(dest);
tcg_gen_lookup_and_goto_ptr();
--
2.51.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] accel/tcg: Name gen_goto_tb()'s TB slot index as @tb_slot_idx
2025-10-10 3:17 [PATCH] accel/tcg: Name gen_goto_tb()'s TB slot index as @tb_slot_idx Philippe Mathieu-Daudé
@ 2025-10-15 16:52 ` Philippe Mathieu-Daudé
2025-10-15 17:32 ` Richard Henderson
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-15 16:52 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson, Anton Johansson, Pierrick Bouvier
ping?
On 10/10/25 05:17, Philippe Mathieu-Daudé wrote:
> tcg_gen_goto_tb() takes an unsigned index to the TB slot (0 or 1).
> Declare the argument as unsigned and rename it as @tb_slot_idx
> (which is more descriptive than @n) on all targets.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/alpha/translate.c | 8 ++++----
> target/arm/tcg/translate-a64.c | 8 ++++----
> target/arm/tcg/translate.c | 8 ++++----
> target/avr/translate.c | 7 ++++---
> target/hexagon/translate.c | 8 ++++----
> target/loongarch/tcg/translate.c | 7 ++++---
> target/microblaze/translate.c | 7 ++++---
> target/mips/tcg/translate.c | 7 ++++---
> target/ppc/translate.c | 7 ++++---
> target/riscv/translate.c | 9 +++++----
> target/rx/translate.c | 7 ++++---
> target/sh4/translate.c | 7 ++++---
> target/sparc/translate.c | 6 +++---
> target/tricore/translate.c | 7 ++++---
> 14 files changed, 56 insertions(+), 47 deletions(-)
>
> diff --git a/target/alpha/translate.c b/target/alpha/translate.c
> index f11b382438c..a492520075e 100644
> --- a/target/alpha/translate.c
> +++ b/target/alpha/translate.c
> @@ -436,18 +436,18 @@ static DisasJumpType gen_store_conditional(DisasContext *ctx, int ra, int rb,
> return DISAS_NEXT;
> }
>
> -static void gen_goto_tb(DisasContext *ctx, int idx, int32_t disp)
> +static void gen_goto_tb(DisasContext *ctx, unsigned tb_slot_idx, int32_t disp)
> {
> if (translator_use_goto_tb(&ctx->base, ctx->base.pc_next + disp)) {
> /* With PCREL, PC must always be up-to-date. */
> if (ctx->pcrel) {
> gen_pc_disp(ctx, cpu_pc, disp);
> - tcg_gen_goto_tb(idx);
> + tcg_gen_goto_tb(tb_slot_idx);
> } else {
> - tcg_gen_goto_tb(idx);
> + tcg_gen_goto_tb(tb_slot_idx);
> gen_pc_disp(ctx, cpu_pc, disp);
> }
> - tcg_gen_exit_tb(ctx->base.tb, idx);
> + tcg_gen_exit_tb(ctx->base.tb, tb_slot_idx);
> } else {
> gen_pc_disp(ctx, cpu_pc, disp);
> tcg_gen_lookup_and_goto_ptr();
> diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
> index a0e3300231f..20c2a5b4861 100644
> --- a/target/arm/tcg/translate-a64.c
> +++ b/target/arm/tcg/translate-a64.c
> @@ -471,7 +471,7 @@ static inline bool use_goto_tb(DisasContext *s, uint64_t dest)
> return translator_use_goto_tb(&s->base, dest);
> }
>
> -static void gen_goto_tb(DisasContext *s, int n, int64_t diff)
> +static void gen_goto_tb(DisasContext *s, unsigned tb_slot_idx, int64_t diff)
> {
> if (use_goto_tb(s, s->pc_curr + diff)) {
> /*
> @@ -484,12 +484,12 @@ static void gen_goto_tb(DisasContext *s, int n, int64_t diff)
> */
> if (tb_cflags(s->base.tb) & CF_PCREL) {
> gen_a64_update_pc(s, diff);
> - tcg_gen_goto_tb(n);
> + tcg_gen_goto_tb(tb_slot_idx);
> } else {
> - tcg_gen_goto_tb(n);
> + tcg_gen_goto_tb(tb_slot_idx);
> gen_a64_update_pc(s, diff);
> }
> - tcg_gen_exit_tb(s->base.tb, n);
> + tcg_gen_exit_tb(s->base.tb, tb_slot_idx);
> s->base.is_jmp = DISAS_NORETURN;
> } else {
> gen_a64_update_pc(s, diff);
> diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
> index e62dcc5d85d..51654b0b91d 100644
> --- a/target/arm/tcg/translate.c
> +++ b/target/arm/tcg/translate.c
> @@ -1259,7 +1259,7 @@ static void gen_goto_ptr(void)
> * cpu_loop_exec. Any live exit_requests will be processed as we
> * enter the next TB.
> */
> -static void gen_goto_tb(DisasContext *s, int n, target_long diff)
> +static void gen_goto_tb(DisasContext *s, unsigned tb_slot_idx, target_long diff)
> {
> if (translator_use_goto_tb(&s->base, s->pc_curr + diff)) {
> /*
> @@ -1272,12 +1272,12 @@ static void gen_goto_tb(DisasContext *s, int n, target_long diff)
> */
> if (tb_cflags(s->base.tb) & CF_PCREL) {
> gen_update_pc(s, diff);
> - tcg_gen_goto_tb(n);
> + tcg_gen_goto_tb(tb_slot_idx);
> } else {
> - tcg_gen_goto_tb(n);
> + tcg_gen_goto_tb(tb_slot_idx);
> gen_update_pc(s, diff);
> }
> - tcg_gen_exit_tb(s->base.tb, n);
> + tcg_gen_exit_tb(s->base.tb, tb_slot_idx);
> } else {
> gen_update_pc(s, diff);
> gen_goto_ptr();
> diff --git a/target/avr/translate.c b/target/avr/translate.c
> index 804b0b21dbd..ef6f655a458 100644
> --- a/target/avr/translate.c
> +++ b/target/avr/translate.c
> @@ -981,14 +981,15 @@ static void gen_pop_ret(DisasContext *ctx, TCGv ret)
> }
> }
>
> -static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
> +static void gen_goto_tb(DisasContext *ctx, unsigned tb_slot_idx,
> + target_ulong dest)
> {
> const TranslationBlock *tb = ctx->base.tb;
>
> if (translator_use_goto_tb(&ctx->base, dest)) {
> - tcg_gen_goto_tb(n);
> + tcg_gen_goto_tb(tb_slot_idx);
> tcg_gen_movi_i32(cpu_pc, dest);
> - tcg_gen_exit_tb(tb, n);
> + tcg_gen_exit_tb(tb, tb_slot_idx);
> } else {
> tcg_gen_movi_i32(cpu_pc, dest);
> tcg_gen_lookup_and_goto_ptr();
> diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
> index 02fd40c160f..50766eafe27 100644
> --- a/target/hexagon/translate.c
> +++ b/target/hexagon/translate.c
> @@ -133,15 +133,15 @@ static bool use_goto_tb(DisasContext *ctx, target_ulong dest)
> return translator_use_goto_tb(&ctx->base, dest);
> }
>
> -static void gen_goto_tb(DisasContext *ctx, int idx, target_ulong dest, bool
> - move_to_pc)
> +static void gen_goto_tb(DisasContext *ctx, unsigned tb_slot_idx,
> + target_ulong dest, bool move_to_pc)
> {
> if (use_goto_tb(ctx, dest)) {
> - tcg_gen_goto_tb(idx);
> + tcg_gen_goto_tb(tb_slot_idx);
> if (move_to_pc) {
> tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], dest);
> }
> - tcg_gen_exit_tb(ctx->base.tb, idx);
> + tcg_gen_exit_tb(ctx->base.tb, tb_slot_idx);
> } else {
> if (move_to_pc) {
> tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], dest);
> diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/translate.c
> index 53a0b4c3ce9..57c3b8c4bb2 100644
> --- a/target/loongarch/tcg/translate.c
> +++ b/target/loongarch/tcg/translate.c
> @@ -99,16 +99,17 @@ void generate_exception(DisasContext *ctx, int excp)
> ctx->base.is_jmp = DISAS_NORETURN;
> }
>
> -static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
> +static void gen_goto_tb(DisasContext *ctx, unsigned tb_slot_idx,
> + target_ulong dest)
> {
> if (ctx->va32) {
> dest = (uint32_t) dest;
> }
>
> if (translator_use_goto_tb(&ctx->base, dest)) {
> - tcg_gen_goto_tb(n);
> + tcg_gen_goto_tb(tb_slot_idx);
> tcg_gen_movi_tl(cpu_pc, dest);
> - tcg_gen_exit_tb(ctx->base.tb, n);
> + tcg_gen_exit_tb(ctx->base.tb, tb_slot_idx);
> } else {
> tcg_gen_movi_tl(cpu_pc, dest);
> tcg_gen_lookup_and_goto_ptr();
> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index 5098a1db4dc..3dd74b021e8 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -116,12 +116,13 @@ static void gen_raise_hw_excp(DisasContext *dc, uint32_t esr_ec)
> gen_raise_exception_sync(dc, EXCP_HW_EXCP);
> }
>
> -static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
> +static void gen_goto_tb(DisasContext *dc, unsigned tb_slot_idx,
> + target_ulong dest)
> {
> if (translator_use_goto_tb(&dc->base, dest)) {
> - tcg_gen_goto_tb(n);
> + tcg_gen_goto_tb(tb_slot_idx);
> tcg_gen_movi_i32(cpu_pc, dest);
> - tcg_gen_exit_tb(dc->base.tb, n);
> + tcg_gen_exit_tb(dc->base.tb, tb_slot_idx);
> } else {
> tcg_gen_movi_i32(cpu_pc, dest);
> tcg_gen_lookup_and_goto_ptr();
> diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
> index d91d6efe02c..54849e9ff1a 100644
> --- a/target/mips/tcg/translate.c
> +++ b/target/mips/tcg/translate.c
> @@ -4362,12 +4362,13 @@ static void gen_trap(DisasContext *ctx, uint32_t opc,
> }
> }
>
> -static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
> +static void gen_goto_tb(DisasContext *ctx, unsigned tb_slot_idx,
> + target_ulong dest)
> {
> if (translator_use_goto_tb(&ctx->base, dest)) {
> - tcg_gen_goto_tb(n);
> + tcg_gen_goto_tb(tb_slot_idx);
> gen_save_pc(dest);
> - tcg_gen_exit_tb(ctx->base.tb, n);
> + tcg_gen_exit_tb(ctx->base.tb, tb_slot_idx);
> } else {
> gen_save_pc(dest);
> tcg_gen_lookup_and_goto_ptr();
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index d422789a1d0..17e6d07c8c2 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -3668,16 +3668,17 @@ static void gen_lookup_and_goto_ptr(DisasContext *ctx)
> }
>
> /*** Branch ***/
> -static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
> +static void gen_goto_tb(DisasContext *ctx, unsigned tb_slot_idx,
> + target_ulong dest)
> {
> if (NARROW_MODE(ctx)) {
> dest = (uint32_t) dest;
> }
> if (use_goto_tb(ctx, dest)) {
> pmu_count_insns(ctx);
> - tcg_gen_goto_tb(n);
> + tcg_gen_goto_tb(tb_slot_idx);
> tcg_gen_movi_tl(cpu_nip, dest & ~3);
> - tcg_gen_exit_tb(ctx->base.tb, n);
> + tcg_gen_exit_tb(ctx->base.tb, tb_slot_idx);
> } else {
> tcg_gen_movi_tl(cpu_nip, dest & ~3);
> gen_lookup_and_goto_ptr(ctx);
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 6fc06c71f51..9a53aecbfe9 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -286,7 +286,8 @@ static void exit_tb(DisasContext *ctx)
> tcg_gen_exit_tb(NULL, 0);
> }
>
> -static void gen_goto_tb(DisasContext *ctx, int n, target_long diff)
> +static void gen_goto_tb(DisasContext *ctx, unsigned tb_slot_idx,
> + target_long diff)
> {
> target_ulong dest = ctx->base.pc_next + diff;
>
> @@ -305,12 +306,12 @@ static void gen_goto_tb(DisasContext *ctx, int n, target_long diff)
> */
> if (tb_cflags(ctx->base.tb) & CF_PCREL) {
> gen_update_pc(ctx, diff);
> - tcg_gen_goto_tb(n);
> + tcg_gen_goto_tb(tb_slot_idx);
> } else {
> - tcg_gen_goto_tb(n);
> + tcg_gen_goto_tb(tb_slot_idx);
> gen_update_pc(ctx, diff);
> }
> - tcg_gen_exit_tb(ctx->base.tb, n);
> + tcg_gen_exit_tb(ctx->base.tb, tb_slot_idx);
> } else {
> gen_update_pc(ctx, diff);
> lookup_and_goto_ptr(ctx);
> diff --git a/target/rx/translate.c b/target/rx/translate.c
> index 19a9584a829..5fc589c706b 100644
> --- a/target/rx/translate.c
> +++ b/target/rx/translate.c
> @@ -147,12 +147,13 @@ void rx_cpu_dump_state(CPUState *cs, FILE *f, int flags)
> }
> }
>
> -static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
> +static void gen_goto_tb(DisasContext *dc, unsigned tb_slot_idx,
> + target_ulong dest)
> {
> if (translator_use_goto_tb(&dc->base, dest)) {
> - tcg_gen_goto_tb(n);
> + tcg_gen_goto_tb(tb_slot_idx);
> tcg_gen_movi_i32(cpu_pc, dest);
> - tcg_gen_exit_tb(dc->base.tb, n);
> + tcg_gen_exit_tb(dc->base.tb, tb_slot_idx);
> } else {
> tcg_gen_movi_i32(cpu_pc, dest);
> tcg_gen_lookup_and_goto_ptr();
> diff --git a/target/sh4/translate.c b/target/sh4/translate.c
> index 70fd13aa3f5..137b75a4fb2 100644
> --- a/target/sh4/translate.c
> +++ b/target/sh4/translate.c
> @@ -231,12 +231,13 @@ static bool use_goto_tb(DisasContext *ctx, target_ulong dest)
> return translator_use_goto_tb(&ctx->base, dest);
> }
>
> -static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
> +static void gen_goto_tb(DisasContext *ctx, unsigned tb_slot_idx,
> + target_ulong dest)
> {
> if (use_goto_tb(ctx, dest)) {
> - tcg_gen_goto_tb(n);
> + tcg_gen_goto_tb(tb_slot_idx);
> tcg_gen_movi_i32(cpu_pc, dest);
> - tcg_gen_exit_tb(ctx->base.tb, n);
> + tcg_gen_exit_tb(ctx->base.tb, tb_slot_idx);
> } else {
> tcg_gen_movi_i32(cpu_pc, dest);
> if (use_exit_tb(ctx)) {
> diff --git a/target/sparc/translate.c b/target/sparc/translate.c
> index 810e2491a61..d6b599b71fe 100644
> --- a/target/sparc/translate.c
> +++ b/target/sparc/translate.c
> @@ -363,15 +363,15 @@ static bool use_goto_tb(DisasContext *s, target_ulong pc, target_ulong npc)
> translator_use_goto_tb(&s->base, npc);
> }
>
> -static void gen_goto_tb(DisasContext *s, int tb_num,
> +static void gen_goto_tb(DisasContext *s, unsigned tb_slot_idx,
> target_ulong pc, target_ulong npc)
> {
> if (use_goto_tb(s, pc, npc)) {
> /* jump to same page: we can use a direct jump */
> - tcg_gen_goto_tb(tb_num);
> + tcg_gen_goto_tb(tb_slot_idx);
> tcg_gen_movi_tl(cpu_pc, pc);
> tcg_gen_movi_tl(cpu_npc, npc);
> - tcg_gen_exit_tb(s->base.tb, tb_num);
> + tcg_gen_exit_tb(s->base.tb, tb_slot_idx);
> } else {
> /* jump to another page: we can use an indirect jump */
> tcg_gen_movi_tl(cpu_pc, pc);
> diff --git a/target/tricore/translate.c b/target/tricore/translate.c
> index 3d0e7a10bd8..7c6e3095971 100644
> --- a/target/tricore/translate.c
> +++ b/target/tricore/translate.c
> @@ -2816,12 +2816,13 @@ static inline void gen_save_pc(target_ulong pc)
> tcg_gen_movi_tl(cpu_PC, pc);
> }
>
> -static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
> +static void gen_goto_tb(DisasContext *ctx, unsigned tb_slot_index,
> + target_ulong dest)
> {
> if (translator_use_goto_tb(&ctx->base, dest)) {
> - tcg_gen_goto_tb(n);
> + tcg_gen_goto_tb(tb_slot_index);
> gen_save_pc(dest);
> - tcg_gen_exit_tb(ctx->base.tb, n);
> + tcg_gen_exit_tb(ctx->base.tb, tb_slot_index);
> } else {
> gen_save_pc(dest);
> tcg_gen_lookup_and_goto_ptr();
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] accel/tcg: Name gen_goto_tb()'s TB slot index as @tb_slot_idx
2025-10-10 3:17 [PATCH] accel/tcg: Name gen_goto_tb()'s TB slot index as @tb_slot_idx Philippe Mathieu-Daudé
2025-10-15 16:52 ` Philippe Mathieu-Daudé
@ 2025-10-15 17:32 ` Richard Henderson
2025-10-15 18:04 ` Pierrick Bouvier
2025-10-16 12:14 ` Philippe Mathieu-Daudé
3 siblings, 0 replies; 5+ messages in thread
From: Richard Henderson @ 2025-10-15 17:32 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
On 10/9/25 20:17, Philippe Mathieu-Daudé wrote:
> tcg_gen_goto_tb() takes an unsigned index to the TB slot (0 or 1).
> Declare the argument as unsigned and rename it as @tb_slot_idx
> (which is more descriptive than @n) on all targets.
>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---
> target/alpha/translate.c | 8 ++++----
> target/arm/tcg/translate-a64.c | 8 ++++----
> target/arm/tcg/translate.c | 8 ++++----
> target/avr/translate.c | 7 ++++---
> target/hexagon/translate.c | 8 ++++----
> target/loongarch/tcg/translate.c | 7 ++++---
> target/microblaze/translate.c | 7 ++++---
> target/mips/tcg/translate.c | 7 ++++---
> target/ppc/translate.c | 7 ++++---
> target/riscv/translate.c | 9 +++++----
> target/rx/translate.c | 7 ++++---
> target/sh4/translate.c | 7 ++++---
> target/sparc/translate.c | 6 +++---
> target/tricore/translate.c | 7 ++++---
> 14 files changed, 56 insertions(+), 47 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] accel/tcg: Name gen_goto_tb()'s TB slot index as @tb_slot_idx
2025-10-10 3:17 [PATCH] accel/tcg: Name gen_goto_tb()'s TB slot index as @tb_slot_idx Philippe Mathieu-Daudé
2025-10-15 16:52 ` Philippe Mathieu-Daudé
2025-10-15 17:32 ` Richard Henderson
@ 2025-10-15 18:04 ` Pierrick Bouvier
2025-10-16 12:14 ` Philippe Mathieu-Daudé
3 siblings, 0 replies; 5+ messages in thread
From: Pierrick Bouvier @ 2025-10-15 18:04 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Richard Henderson
On 10/9/25 8:17 PM, Philippe Mathieu-Daudé wrote:
> tcg_gen_goto_tb() takes an unsigned index to the TB slot (0 or 1).
> Declare the argument as unsigned and rename it as @tb_slot_idx
> (which is more descriptive than @n) on all targets.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/alpha/translate.c | 8 ++++----
> target/arm/tcg/translate-a64.c | 8 ++++----
> target/arm/tcg/translate.c | 8 ++++----
> target/avr/translate.c | 7 ++++---
> target/hexagon/translate.c | 8 ++++----
> target/loongarch/tcg/translate.c | 7 ++++---
> target/microblaze/translate.c | 7 ++++---
> target/mips/tcg/translate.c | 7 ++++---
> target/ppc/translate.c | 7 ++++---
> target/riscv/translate.c | 9 +++++----
> target/rx/translate.c | 7 ++++---
> target/sh4/translate.c | 7 ++++---
> target/sparc/translate.c | 6 +++---
> target/tricore/translate.c | 7 ++++---
> 14 files changed, 56 insertions(+), 47 deletions(-)
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] accel/tcg: Name gen_goto_tb()'s TB slot index as @tb_slot_idx
2025-10-10 3:17 [PATCH] accel/tcg: Name gen_goto_tb()'s TB slot index as @tb_slot_idx Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2025-10-15 18:04 ` Pierrick Bouvier
@ 2025-10-16 12:14 ` Philippe Mathieu-Daudé
3 siblings, 0 replies; 5+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-16 12:14 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson
On 10/10/25 05:17, Philippe Mathieu-Daudé wrote:
> tcg_gen_goto_tb() takes an unsigned index to the TB slot (0 or 1).
> Declare the argument as unsigned and rename it as @tb_slot_idx
> (which is more descriptive than @n) on all targets.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/alpha/translate.c | 8 ++++----
> target/arm/tcg/translate-a64.c | 8 ++++----
> target/arm/tcg/translate.c | 8 ++++----
> target/avr/translate.c | 7 ++++---
> target/hexagon/translate.c | 8 ++++----
> target/loongarch/tcg/translate.c | 7 ++++---
> target/microblaze/translate.c | 7 ++++---
> target/mips/tcg/translate.c | 7 ++++---
> target/ppc/translate.c | 7 ++++---
> target/riscv/translate.c | 9 +++++----
> target/rx/translate.c | 7 ++++---
> target/sh4/translate.c | 7 ++++---
> target/sparc/translate.c | 6 +++---
> target/tricore/translate.c | 7 ++++---
> 14 files changed, 56 insertions(+), 47 deletions(-)
Patch queued, thanks.
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2025-10-16 12:15 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2025-10-10 3:17 [PATCH] accel/tcg: Name gen_goto_tb()'s TB slot index as @tb_slot_idx Philippe Mathieu-Daudé
2025-10-15 16:52 ` Philippe Mathieu-Daudé
2025-10-15 17:32 ` Richard Henderson
2025-10-15 18:04 ` Pierrick Bouvier
2025-10-16 12:14 ` Philippe Mathieu-Daudé
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