qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Richard Henderson <richard.henderson@linaro.org>
To: Alistair Francis <Alistair.Francis@wdc.com>,
	"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
	"qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>
Cc: "alistair23@gmail.com" <alistair23@gmail.com>
Subject: Re: [Qemu-devel] [RFC v1 16/23] riscv: tcg-target: Add slowpath load and store instructions
Date: Fri, 16 Nov 2018 10:24:45 +0100	[thread overview]
Message-ID: <f56a1b1c-8cc8-7e85-c88b-3894e4628d6b@linaro.org> (raw)
In-Reply-To: <bd8f5c781f7086c5b26e1bd4c8e6570b5534b22d.1542321076.git.alistair.francis@wdc.com>

On 11/15/18 11:36 PM, Alistair Francis wrote:
> +static void tcg_out_mb(TCGContext *s, TCGArg a0)
> +{
> +    static const RISCVInsn fence[] = {
> +        [0 ... TCG_MO_ALL] = OPC_FENCE_RW_RW,
> +        [TCG_MO_LD_LD]     = OPC_FENCE_R_R,
> +        [TCG_MO_ST_LD]     = OPC_FENCE_W_R,
> +        [TCG_MO_LD_ST]     = OPC_FENCE_R_W,
> +        [TCG_MO_ST_ST]     = OPC_FENCE_W_W,
> +        [TCG_BAR_LDAQ]     = OPC_FENCE_R_RW,
> +        [TCG_BAR_STRL]     = OPC_FENCE_RW_W,
> +        [TCG_BAR_SC]       = OPC_FENCE_RW_RW,
> +    };
> +    tcg_out32(s, fence[a0 & TCG_MO_ALL]);
> +}
> +

TCG_MO_* and TCG_BAR_* are two different bitmasks, or'ed together.
Which you've separated by "& TCG_MO_ALL".  Thus the TCG_BAR_* constants should
not appear in this table.


> +static void * const qemu_ld_helpers[16] = {
> +    [MO_UB]   = helper_ret_ldub_mmu,
> +    [MO_SB]   = helper_ret_ldsb_mmu,
> +    [MO_LEUW] = helper_le_lduw_mmu,
> +    [MO_LESW] = helper_le_ldsw_mmu,
> +    [MO_LEUL] = helper_le_ldul_mmu,
> +    [MO_LESL] = helper_le_ldsl_mmu,
> +    [MO_LEQ]  = helper_le_ldq_mmu,
> +    [MO_BEUW] = helper_be_lduw_mmu,
> +    [MO_BESW] = helper_be_ldsw_mmu,
> +    [MO_BEUL] = helper_be_ldul_mmu,
> +    [MO_BESL] = helper_be_ldsl_mmu,
> +    [MO_BEQ]  = helper_be_ldq_mmu,
> +};

The LESL and BESL functions will not be present for rv32 -> link error.  Here
you do need an ifdef.

> +        } else {
> +            adj = cmp_off - sextract32(cmp_off, 0, 12);
> +            tcg_debug_assert(add_off - adj >= -0x1000
> +                             && add_off - adj < 0x1000);
> +
> +            tcg_out_opc_upper(s, OPC_LUI, base, adj);
> +            tcg_out_opc_reg(s, OPC_ADD, base, TCG_REG_ZERO, TCG_AREG0);

base, base, TCG_AREG0.

> +    /* Compare masked address with the TLB entry. */
> +    label_ptr[0] = s->code_ptr;
> +    tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0);

Another case of a potential out-of-range branch.

It might be worthwhile to move all of this out-of-line from the start, where
that branch will always be short.  See

http://lists.nongnu.org/archive/html/qemu-devel/2018-11/msg02234.html


r~

  reply	other threads:[~2018-11-16  9:24 UTC|newest]

Thread overview: 65+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-15 22:33 [Qemu-devel] [RFC v1 00/23] Add RISC-V TCG backend support Alistair Francis
2018-11-15 22:34 ` [Qemu-devel] [RFC v1 01/23] elf.h: Add the RISCV ELF magic numbers Alistair Francis
2018-11-16  7:46   ` Richard Henderson
2018-11-15 22:34 ` [Qemu-devel] [RFC v1 02/23] linux-user: Add host dependency for RISC-V 32-bit Alistair Francis
2018-11-16  7:46   ` Richard Henderson
2018-11-16  7:47   ` Richard Henderson
2018-11-15 22:34 ` [Qemu-devel] [RFC v1 03/23] linux-user: Add host dependency for RISC-V 64-bit Alistair Francis
2018-11-16  7:57   ` Richard Henderson
2018-11-15 22:34 ` [Qemu-devel] [RFC v1 04/23] exec: Add RISC-V GCC poison macro Alistair Francis
2018-11-16  7:47   ` Richard Henderson
2018-11-15 22:34 ` [Qemu-devel] [RFC v1 05/23] riscv: Add the tcg-target header file Alistair Francis
2018-11-16  7:57   ` Richard Henderson
2018-11-16 17:20   ` Richard Henderson
2018-11-15 22:34 ` [Qemu-devel] [RFC v1 06/23] riscv: Add the tcg target registers Alistair Francis
2018-11-16  7:58   ` Richard Henderson
2018-11-15 22:34 ` [Qemu-devel] [RFC v1 07/23] riscv: tcg-target: Regiser the JIT Alistair Francis
2018-11-16  7:59   ` Richard Henderson
2018-11-15 22:35 ` [Qemu-devel] [RFC v1 08/23] riscv: tcg-target: Add support for the constraints Alistair Francis
2018-11-16  8:13   ` Richard Henderson
2018-11-15 22:35 ` [Qemu-devel] [RFC v1 09/23] riscv: tcg-target: Add the immediate encoders Alistair Francis
2018-11-16  8:26   ` Richard Henderson
2018-11-15 22:35 ` [Qemu-devel] [RFC v1 10/23] riscv: tcg-target: Add the instruction emitters Alistair Francis
2018-11-16  8:27   ` Richard Henderson
2018-11-15 22:35 ` [Qemu-devel] [RFC v1 11/23] riscv: tcg-target: Add the relocation functions Alistair Francis
2018-11-16  8:33   ` Richard Henderson
2018-11-21  1:15     ` Alistair Francis
2018-11-21  7:25       ` Richard Henderson
2018-11-21 15:53       ` Palmer Dabbelt
2018-11-21 17:01         ` Richard Henderson
2018-11-15 22:35 ` [Qemu-devel] [RFC v1 12/23] riscv: tcg-target: Add the mov and movi instruction Alistair Francis
2018-11-16  8:55   ` Richard Henderson
2018-11-15 22:35 ` [Qemu-devel] [RFC v1 13/23] riscv: tcg-target: Add the extract instructions Alistair Francis
2018-11-16  8:56   ` Richard Henderson
2018-11-15 22:36 ` [Qemu-devel] [RFC v1 14/23] riscv: tcg-target: Add the out load and store instructions Alistair Francis
2018-11-16  8:59   ` Richard Henderson
2018-11-15 22:36 ` [Qemu-devel] [RFC v1 15/23] riscv: tcg-target: Add branch and jump instructions Alistair Francis
2018-11-16  9:14   ` Richard Henderson
2018-11-20 23:49     ` Alistair Francis
2018-11-21  7:40       ` Richard Henderson
2018-11-26 22:58         ` Alistair Francis
2018-11-15 22:36 ` [Qemu-devel] [RFC v1 16/23] riscv: tcg-target: Add slowpath load and store instructions Alistair Francis
2018-11-16  9:24   ` Richard Henderson [this message]
2018-11-21  0:18     ` Alistair Francis
2018-11-21  7:43       ` Richard Henderson
2018-11-15 22:36 ` [Qemu-devel] [RFC v1 17/23] riscv: tcg-target: Add direct " Alistair Francis
2018-11-16 17:10   ` Richard Henderson
2018-11-19 23:06     ` Alistair Francis
2018-11-20  6:57       ` Richard Henderson
2018-11-15 22:36 ` [Qemu-devel] [RFC v1 18/23] riscv: tcg-target: Add the out op decoder Alistair Francis
2018-11-16 17:22   ` Richard Henderson
2018-11-15 22:36 ` [Qemu-devel] [RFC v1 19/23] riscv: tcg-target: Add the prologue generation Alistair Francis
2018-11-16 17:25   ` Richard Henderson
2018-11-15 22:36 ` [Qemu-devel] [RFC v1 20/23] riscv: tcg-target: Add the target init code Alistair Francis
2018-11-16 17:26   ` Richard Henderson
2018-11-19 23:04     ` Alistair Francis
2018-11-20  6:55       ` Richard Henderson
2018-11-20 23:22         ` Alistair Francis
2018-11-15 22:37 ` [Qemu-devel] [RFC v1 21/23] tcg: Add RISC-V cpu signal handler Alistair Francis
2018-11-16 17:27   ` Richard Henderson
2018-11-16 17:29   ` Richard Henderson
2018-11-15 22:37 ` [Qemu-devel] [RFC v1 22/23] dias: Add RISC-V support Alistair Francis
2018-11-16 17:29   ` Richard Henderson
2018-11-15 22:37 ` [Qemu-devel] [RFC v1 23/23] configure: Add support for building RISC-V host Alistair Francis
2018-11-16 17:30   ` Richard Henderson
2018-11-16  8:31 ` [Qemu-devel] [RFC v1 00/23] Add RISC-V TCG backend support no-reply

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=f56a1b1c-8cc8-7e85-c88b-3894e4628d6b@linaro.org \
    --to=richard.henderson@linaro.org \
    --cc=Alistair.Francis@wdc.com \
    --cc=alistair23@gmail.com \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-riscv@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).