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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-477a9739964sm82685845e9.1.2025.11.20.23.06.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 20 Nov 2025 23:06:28 -0800 (PST) Message-ID: Date: Fri, 21 Nov 2025 08:06:25 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 1/1] hw/pci-host/aspeed_pcie: Update ASPEED PCIe Root Port capabilities and enable MSI to support hotplug Content-Language: en-US To: Jamin Lin , =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" Cc: troy_lee@aspeedtech.com, nabihestefan@google.com References: <20251121050108.3407445-1-jamin_lin@aspeedtech.com> <20251121050108.3407445-2-jamin_lin@aspeedtech.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20251121050108.3407445-2-jamin_lin@aspeedtech.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=philmd@linaro.org; helo=mail-ed1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 21/11/25 06:01, Jamin Lin via wrote: > This patch updates the ASPEED PCIe Root Port capability layout and interrupt > handling to match the hardware-defined capability structure as documented in > the PCI Express Controller (PCIE) chapter of the ASPEED SoC datasheet. > > The following capability offsets and fields are now aligned with the actual > hardware implementation (validated using EVB config-space dumps via > 'lspci -s -vvv'): > > - Added MSI capability at offset 0x50 and enabled 1-vector MSI support > - Added PCI Express Capability structure at offset 0x80 > - Added Secondary Subsystem Vendor ID (SSVID) at offset 0xC0 > - Added AER capability at offset 0x100 > - Implemented aer_vector() callback and MSI init/uninit hooks > - Updated Root Port SSID to 0x1150 to reflect the platform default > > Enabling MSI is required for proper PCIe Hotplug event signaling. This change > improves correctness and ensures QEMU Root Port behavior matches the behavior > of ASPEED hardware and downstream kernel expectations. > > Signed-off-by: Jamin Lin > --- > hw/pci-host/aspeed_pcie.c | 40 ++++++++++++++++++++++++++++++++++++++- > 1 file changed, 39 insertions(+), 1 deletion(-) Reviewed-by: Philippe Mathieu-Daudé