From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Luc Michel <luc.michel@amd.com>,
qemu-devel@nongnu.org, qemu-arm@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>,
Francisco Iglesias <francisco.iglesias@amd.com>,
"Edgar E . Iglesias" <edgar.iglesias@amd.com>,
Alistair Francis <alistair@alistair23.me>,
Frederic Konrad <frederic.konrad@amd.com>,
Sai Pavan Boddu <sai.pavan.boddu@amd.com>
Subject: Re: [PATCH v4 36/47] hw/misc/xlnx-versal-crl: add the versal2 version
Date: Fri, 29 Aug 2025 00:22:44 +0200 [thread overview]
Message-ID: <f5aeb950-47b6-47e2-8b6d-cdd01004f1f6@linaro.org> (raw)
In-Reply-To: <20250822151614.187856-37-luc.michel@amd.com>
On 22/8/25 17:16, Luc Michel wrote:
> Add the versal2 version of the CRL device. For the implemented part, it
> is similar to the versal version but drives reset line of more devices.
>
> Signed-off-by: Luc Michel <luc.michel@amd.com>
> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
> ---
> include/hw/arm/xlnx-versal-version.h | 1 +
> include/hw/misc/xlnx-versal-crl.h | 329 ++++++++++++++++++++++
> hw/misc/xlnx-versal-crl.c | 392 +++++++++++++++++++++++++++
> 3 files changed, 722 insertions(+)
> +static DeviceState **versal2_decode_periph_rst(XlnxVersalCRLBase *s,
> + hwaddr addr, size_t *count)
> +{
> + size_t idx;
> + XlnxVersal2CRL *xvc = XLNX_VERSAL2_CRL(s);
> +
> + *count = 1;
> +
> + switch (addr) {
> + case A_VERSAL2_RST_RPU_A ... A_VERSAL2_RST_RPU_E:
> + idx = (addr - A_VERSAL2_RST_RPU_A) / sizeof(uint32_t);
> + idx *= 2; /* two RPUs per RST_RPU_x registers */
> + return xvc->cfg.rpu + idx;
> +
> + case A_VERSAL2_RST_ADMA:
> + /* A single register fans out to all DMA reset inputs */
> + *count = ARRAY_SIZE(xvc->cfg.adma);
> + return xvc->cfg.adma;
> +
> + case A_VERSAL2_RST_SDMA:
> + *count = ARRAY_SIZE(xvc->cfg.sdma);
> + return xvc->cfg.sdma;
> +
> + case A_VERSAL2_RST_UART0 ... A_VERSAL2_RST_UART1:
> + idx = (addr - A_VERSAL2_RST_UART0) / sizeof(uint32_t);
> + return xvc->cfg.uart + idx;
> +
> + case A_VERSAL2_RST_GEM0 ... A_VERSAL2_RST_GEM1:
> + idx = (addr - A_VERSAL2_RST_GEM0) / sizeof(uint32_t);
> + return xvc->cfg.gem + idx;
> +
> + case A_VERSAL2_RST_USB0 ... A_VERSAL2_RST_USB1:
> + idx = (addr - A_VERSAL2_RST_USB0) / sizeof(uint32_t);
> + return xvc->cfg.usb + idx;
> +
> + case A_VERSAL2_RST_CAN0 ... A_VERSAL2_RST_CAN3:
> + idx = (addr - A_VERSAL2_RST_CAN0) / sizeof(uint32_t);
> + return xvc->cfg.can + idx;
> +
> + default:
> + /* invalid or unimplemented */
> + return NULL;
Can that happen?
Note count=1 when returning. Should we set to 0?
> + }
> +}
Otherwise,
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
next prev parent reply other threads:[~2025-08-30 17:34 UTC|newest]
Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-22 15:15 [PATCH v4 00/47] AMD Versal Gen 2 support Luc Michel
2025-08-22 15:15 ` [PATCH v4 01/47] hw/arm/xlnx-versal: split the xlnx-versal type Luc Michel
2025-08-28 22:07 ` Philippe Mathieu-Daudé
2025-08-22 15:15 ` [PATCH v4 02/47] hw/arm/xlnx-versal: prepare for FDT creation Luc Michel
2025-08-22 15:15 ` [PATCH v4 03/47] hw/arm/xlnx-versal: uart: refactor creation Luc Michel
2025-08-22 15:15 ` [PATCH v4 04/47] hw/arm/xlnx-versal: canfd: " Luc Michel
2025-08-22 15:15 ` [PATCH v4 05/47] hw/arm/xlnx-versal: sdhci: " Luc Michel
2025-08-28 22:19 ` Philippe Mathieu-Daudé
2025-09-02 7:14 ` Luc Michel
2025-08-22 15:15 ` [PATCH v4 06/47] hw/arm/xlnx-versal: gem: " Luc Michel
2025-08-22 15:15 ` [PATCH v4 07/47] hw/arm/xlnx-versal: adma: " Luc Michel
2025-08-22 15:15 ` [PATCH v4 08/47] hw/arm/xlnx-versal: xram: " Luc Michel
2025-08-22 15:15 ` [PATCH v4 09/47] hw/arm/xlnx-versal: usb: " Luc Michel
2025-08-22 15:15 ` [PATCH v4 10/47] hw/arm/xlnx-versal: efuse: " Luc Michel
2025-08-22 15:15 ` [PATCH v4 11/47] hw/arm/xlnx-versal: ospi: " Luc Michel
2025-08-22 15:15 ` [PATCH v4 12/47] hw/arm/xlnx-versal: VersalMap: add support for OR'ed IRQs Luc Michel
2025-08-28 22:10 ` Philippe Mathieu-Daudé
2025-08-22 15:15 ` [PATCH v4 13/47] hw/arm/xlnx-versal: PMC IOU SCLR: refactor creation Luc Michel
2025-08-22 15:15 ` [PATCH v4 14/47] hw/arm/xlnx-versal: bbram: " Luc Michel
2025-08-22 15:15 ` [PATCH v4 15/47] hw/arm/xlnx-versal: trng: " Luc Michel
2025-08-22 15:15 ` [PATCH v4 16/47] hw/arm/xlnx-versal: rtc: " Luc Michel
2025-08-22 15:15 ` [PATCH v4 17/47] hw/arm/xlnx-versal: cfu: " Luc Michel
2025-08-22 15:15 ` [PATCH v4 18/47] hw/arm/xlnx-versal: crl: " Luc Michel
2025-08-22 15:15 ` [PATCH v4 19/47] hw/arm/xlnx-versal-virt: virtio: " Luc Michel
2025-08-22 15:15 ` [PATCH v4 20/47] hw/arm/xlnx-versal: refactor CPU cluster creation Luc Michel
2025-08-28 22:16 ` Philippe Mathieu-Daudé
2025-08-22 15:15 ` [PATCH v4 21/47] hw/arm/xlnx-versal: add the mp_affinity property to the CPU mapping Luc Michel
2025-08-22 15:15 ` [PATCH v4 22/47] hw/arm/xlnx-versal: instantiate the GIC ITS in the APU Luc Michel
2025-08-22 15:15 ` [PATCH v4 23/47] hw/intc/arm_gicv3: Introduce a 'first-cpu-index' property Luc Michel
2025-08-26 19:33 ` Edgar E. Iglesias
2025-08-26 20:05 ` Peter Maydell
2025-09-11 10:45 ` Boddu, Sai Pavan
2025-09-11 14:08 ` Peter Maydell
2025-08-22 15:15 ` [PATCH v4 24/47] hw/arm/xlnx-versal: add support for multiple GICs Luc Michel
2025-08-22 15:15 ` [PATCH v4 25/47] hw/arm/xlnx-versal: add support for GICv2 Luc Michel
2025-08-22 15:15 ` [PATCH v4 26/47] hw/arm/xlnx-versal: rpu: refactor creation Luc Michel
2025-08-22 15:15 ` [PATCH v4 27/47] hw/arm/xlnx-versal: ocm: " Luc Michel
2025-08-22 15:15 ` [PATCH v4 28/47] hw/arm/xlnx-versal: ddr: " Luc Michel
2025-08-22 15:15 ` [PATCH v4 29/47] hw/arm/xlnx-versal: add the versal_get_num_cpu accessor Luc Michel
2025-08-22 15:15 ` [PATCH v4 30/47] hw/misc/xlnx-versal-crl: remove unnecessary include directives Luc Michel
2025-08-22 15:15 ` [PATCH v4 31/47] hw/misc/xlnx-versal-crl: split into base/concrete classes Luc Michel
2025-08-22 15:15 ` [PATCH v4 32/47] hw/misc/xlnx-versal-crl: refactor device reset logic Luc Michel
2025-08-22 15:15 ` [PATCH v4 33/47] hw/arm/xlnx-versal: reconnect the CRL to the other devices Luc Michel
2025-08-22 15:15 ` [PATCH v4 34/47] hw/arm/xlnx-versal: use hw/arm/bsa.h for timer IRQ indices Luc Michel
2025-08-22 15:16 ` [PATCH v4 35/47] hw/arm/xlnx-versal: tidy up Luc Michel
2025-08-22 15:16 ` [PATCH v4 36/47] hw/misc/xlnx-versal-crl: add the versal2 version Luc Michel
2025-08-28 22:22 ` Philippe Mathieu-Daudé [this message]
2025-09-02 7:21 ` Luc Michel
2025-08-22 15:16 ` [PATCH v4 37/47] hw/arm/xlnx-versal: add a per_cluster_gic switch to VersalCpuClusterMap Luc Michel
2025-08-28 22:06 ` Philippe Mathieu-Daudé
2025-08-22 15:16 ` [PATCH v4 38/47] hw/arm/xlnx-versal: add the target field in IRQ descriptor Luc Michel
2025-08-22 15:16 ` [PATCH v4 39/47] target/arm/tcg/cpu64: add the cortex-a78ae CPU Luc Michel
2025-09-11 14:31 ` Peter Maydell
2025-09-12 7:02 ` Luc Michel
2025-08-22 15:16 ` [PATCH v4 40/47] hw/arm/xlnx-versal: add versal2 SoC Luc Michel
2025-08-28 22:04 ` Philippe Mathieu-Daudé
2025-08-22 15:16 ` [PATCH v4 41/47] hw/arm/xlnx-versal-virt: rename the machine to amd-versal-virt Luc Michel
2025-08-22 15:16 ` [PATCH v4 42/47] hw/arm/xlnx-versal-virt: split into base/concrete classes Luc Michel
2025-08-22 15:16 ` [PATCH v4 43/47] hw/arm/xlnx-versal-virt: tidy up Luc Michel
2025-08-22 15:16 ` [PATCH v4 44/47] docs/system/arm/xlnx-versal-virt: update supported devices Luc Michel
2025-08-22 15:16 ` [PATCH v4 45/47] docs/system/arm/xlnx-versal-virt: add a note about dumpdtb Luc Michel
2025-08-22 15:16 ` [PATCH v4 46/47] hw/arm/xlnx-versal-virt: add the xlnx-versal2-virt machine Luc Michel
2025-08-22 15:16 ` [PATCH v4 47/47] tests/functional/test_aarch64_xlnx_versal: test the versal2 machine Luc Michel
2025-09-11 7:08 ` [PATCH v4 00/47] AMD Versal Gen 2 support Luc Michel
2025-09-11 14:05 ` Peter Maydell
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