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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-44092dc229esm31978285e9.40.2025.04.23.09.38.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 23 Apr 2025 09:38:38 -0700 (PDT) Message-ID: Date: Wed, 23 Apr 2025 18:38:37 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 118/147] target/arm/cpu: remove inline stubs for aarch32 emulation To: Pierrick Bouvier , Richard Henderson , qemu-devel@nongnu.org References: <20250422192819.302784-1-richard.henderson@linaro.org> <20250422192819.302784-119-richard.henderson@linaro.org> <4a8da7b6-7773-453d-b704-0991caa3cd97@linaro.org> <41f54ebf-6831-41d6-aa67-f083d6b7b0e8@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <41f54ebf-6831-41d6-aa67-f083d6b7b0e8@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 23/4/25 18:26, Pierrick Bouvier wrote: > On 4/23/25 03:35, Philippe Mathieu-Daudé wrote: >> On 22/4/25 21:27, Richard Henderson wrote: >>> From: Pierrick Bouvier >>> >>> Directly condition associated calls in target/arm/helper.c for now. >>> >>> Reviewed-by: Richard Henderson >>> Signed-off-by: Pierrick Bouvier >>> Signed-off-by: Richard Henderson >>> Message-ID: <20250325045915.994760-23-pierrick.bouvier@linaro.org> >>> --- >>>    target/arm/cpu.h    | 8 -------- >>>    target/arm/helper.c | 6 ++++++ >>>    2 files changed, 6 insertions(+), 8 deletions(-) >>> >>> diff --git a/target/arm/cpu.h b/target/arm/cpu.h >>> index b1c3e46326..c1a0faed3a 100644 >>> --- a/target/arm/cpu.h >>> +++ b/target/arm/cpu.h >>> @@ -1222,7 +1222,6 @@ int >>> arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, >>>     */ >>>    void arm_emulate_firmware_reset(CPUState *cpustate, int target_el); >>> -#ifdef TARGET_AARCH64 >>>    int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, >>> int reg); >>>    int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, >>> int reg); >>>    void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); >>> @@ -1254,13 +1253,6 @@ static inline uint64_t *sve_bswap64(uint64_t >>> *dst, uint64_t *src, int nr) >>>    #endif >>>    } >>> -#else >>> -static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned >>> vq) { } >>> -static inline void aarch64_sve_change_el(CPUARMState *env, int o, >>> -                                         int n, bool a) >>> -{ } >>> -#endif >>> - >>>    void aarch64_sync_32_to_64(CPUARMState *env); >>>    void aarch64_sync_64_to_32(CPUARMState *env); >> >> Should we complete squashing: >> >> -- >8 -- >> diff --git a/target/arm/internals.h b/target/arm/internals.h >> index cf4ab17bc08..f9353887415 100644 >> --- a/target/arm/internals.h >> +++ b/target/arm/internals.h >> @@ -1810,7 +1810,6 @@ static inline uint64_t >> pmu_counter_mask(CPUARMState *env) >>      return (1ULL << 31) | ((1ULL << pmu_num_counters(env)) - 1); >>    } >> >> -#ifdef TARGET_AARCH64 >>    GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *cpu, int >> base_reg); >>    int aarch64_gdb_get_sve_reg(CPUState *cs, GByteArray *buf, int reg); >>    int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf, int reg); >> @@ -1820,7 +1819,6 @@ int aarch64_gdb_get_pauth_reg(CPUState *cs, >> GByteArray *buf, int reg); >>    int aarch64_gdb_set_pauth_reg(CPUState *cs, uint8_t *buf, int reg); >>    int aarch64_gdb_get_tag_ctl_reg(CPUState *cs, GByteArray *buf, int >> reg); >>    int aarch64_gdb_set_tag_ctl_reg(CPUState *cs, uint8_t *buf, int reg); >> -#endif >>    void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); >>    void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp); >>    void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); >> --- >> >> ? >> > > This part of the series focus on hw/arm, so it was not needed to clean > target/arm/internals.h as part of it. > That's why I "pushed" the TARGET_AARCH64 #ifdef to target/arm/helper.c, > allowing to do it later. > I tried to cleanup that completely at the time, as requested by Peter, > but it was pulling too many things, so I just dropped it. > > So I think we should not squash it here. OK, then this patch can be queued on top: https://lore.kernel.org/qemu-devel/20250403235821.9909-37-philmd@linaro.org/