From: Richard Henderson <richard.henderson@linaro.org>
To: Rob Bradford <rbradford@rivosinc.com>, qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Weiwei Li <liweiwei@iscas.ac.cn>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Subject: Re: [PATCH 1/2] target/riscv: Add Zacas ISA extension support
Date: Fri, 2 Jun 2023 20:28:55 -0700 [thread overview]
Message-ID: <f5d8ac15-2e39-b292-af0d-19ab2847dd3e@linaro.org> (raw)
In-Reply-To: <20230602121638.36342-2-rbradford@rivosinc.com>
On 6/2/23 05:16, Rob Bradford wrote:
> +#if TARGET_LONG_BITS == 32
> +static bool trans_amocas_w(DisasContext *ctx, arg_amocas_w *a)
You need to eliminate all of the ifdefs, because we can switch a 64-bit cpu into 32-bit
mode -- get_xl(ctx) shows which mode we are in.
r~
next prev parent reply other threads:[~2023-06-03 3:29 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-02 12:16 RFC: target/riscv: Add support for Zacas extension Rob Bradford
2023-06-02 12:16 ` [PATCH 1/2] target/riscv: Add Zacas ISA extension support Rob Bradford
2023-06-02 15:04 ` Weiwei Li
2023-06-20 15:22 ` Rob Bradford
2023-06-02 15:08 ` Weiwei Li
2023-06-03 3:28 ` Richard Henderson [this message]
2023-06-02 12:16 ` [PATCH 2/2] disas/riscv: Add support for amocas.{w,d,q} instructions Rob Bradford
2023-06-02 12:44 ` [PATCH 2/2] disas/riscv: Add support for amocas.{w, d, q} instructions Rob Bradford
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