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Fri, 21 Nov 2025 19:50:37 -0500 Received: from mxplan5.mail.ovh.net (unknown [10.110.54.239]) by mo552.mail-out.ovh.net (Postfix) with ESMTPS id 4dCqRB4JKKz5vxd; Fri, 21 Nov 2025 22:20:22 +0000 (UTC) Received: from kaod.org (37.59.142.109) by DAG8EX2.mxp5.local (172.16.2.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.61; Fri, 21 Nov 2025 23:20:21 +0100 Authentication-Results: garm.ovh; auth=pass (GARM-109S00389b839f1-458e-4587-8985-f0c954f28545, 20F18A3716404196E6FAACF2E4DECD64BC5092B7) smtp.auth=clg@kaod.org X-OVh-ClientIp: 82.64.250.170 Message-ID: Date: Fri, 21 Nov 2025 23:20:20 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [SPAM] [PATCH v1 1/1] hw/pci-host/aspeed_pcie: Update ASPEED PCIe Root Port capabilities and enable MSI to support hotplug To: Jamin Lin , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , References: <20251121050108.3407445-1-jamin_lin@aspeedtech.com> <20251121050108.3407445-2-jamin_lin@aspeedtech.com> From: =?UTF-8?Q?C=C3=A9dric_Le_Goater?= Content-Language: en-US, fr Autocrypt: addr=clg@kaod.org; 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charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [37.59.142.109] X-ClientProxiedBy: DAG3EX1.mxp5.local (172.16.2.21) To DAG8EX2.mxp5.local (172.16.2.72) X-Ovh-Tracer-GUID: be30a365-2093-4126-8de4-1b53c246e102 X-Ovh-Tracer-Id: 16547632407702965170 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: dmFkZTFKS8Q/iSUMUd6Y3I+pnQM7s4KBxMgvDTzYiWF8NW/vz/dhW5JFYTN1IrGWSKTlTR9G8H291j/OPGi9NzSIQ75YK/GZAq5xNyalnUivYmEUfbslz8R/yfLPYPnhLt117jC3oDz8AXVu299uFLAWZYQeb99X/cnKwwYrXdTC/zuta9t+nz+t8SvPviI/tvBUplnF3ase+pM62iQc3RSAJZ4UaQ2AgT39GfNWkJrzwq+uGFfl6wt313L0qUOt+t61RzmN7hnFstf0f++DrGgYNL9Vysk0SnL+MULqLxL1lZj/nLZcpQ/qxEB+FAe7GtdDA3h3tOSbLCvJU3HIQfs/V731UNEzHzZ5OWfgkn7hKLY3Cx4q4JVSzkCKXSbBclLop34MGfegNtFOz5e3agOB3LCPQU8eX+Mt0bFXH5D32H+C6LQKBtYsI/PHIQDe/4oq6ekigapRmc4fcNvNC/KZZKqPliznht00YVAQRDxZSeo9RQth2PU5YRSG/j46Bo9qhpi5kKeqLebUwZ7sdLEPfzhvFNcN9a4SyrenN9gcws/IhtZp7CVO1VMdJq+NQ8JsdTriTezbnONaojboOD79nLWbxANlUAkwH1b+/LVuClg0dUp4vatD9htuDhpL3PhA8i9THJkfg6otVWZ/65jxP4kzuKAzo6VMpyDD75gz68JBTA DKIM-Signature: a=rsa-sha256; bh=ZEKMy37ICzsTbWB2JeMjKZ7VV/JBa1KK/U94/yKsmO4=; c=relaxed/relaxed; d=kaod.org; h=From; s=ovhmo393970-selector1; t=1763763624; v=1; b=lTY5E+t37nCT/WRxV/A55qLzFrEH36lRaNsFqLXn3cXT2NLyroyEkyb7sPuxY/GqnKy0G0ef dqxIT8baK+/R+x989ZlmgLc6honew5ZcGDIDEol/vcWXz8pBMkXssJbyUGZ8NHNY0zzka4haWPm 86js3BSjZ/Qq6y+bUCRCm4hnJ6k5Is7cEiju3qQ6EQVI0AYpdiWN2iebPoIw33dgdmnoQd9uSPH +9bM9nUcHnyzyej9zHWkKABDbkdam5MhcTi77lw5dotewgJm9Fzy2+B060YtPWpTPwufTnplAjd hfjRE2jb5U0UqZH6om8Xa+po9KkaFgQN6/Bnuos4zrYOw== Received-SPF: pass client-ip=87.98.187.244; envelope-from=clg@kaod.org; helo=10.mo552.mail-out.ovh.net X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/21/25 06:01, Jamin Lin wrote: > This patch updates the ASPEED PCIe Root Port capability layout and interrupt > handling to match the hardware-defined capability structure as documented in > the PCI Express Controller (PCIE) chapter of the ASPEED SoC datasheet. > > The following capability offsets and fields are now aligned with the actual > hardware implementation (validated using EVB config-space dumps via > 'lspci -s -vvv'): > > - Added MSI capability at offset 0x50 and enabled 1-vector MSI support > - Added PCI Express Capability structure at offset 0x80 > - Added Secondary Subsystem Vendor ID (SSVID) at offset 0xC0 > - Added AER capability at offset 0x100 > - Implemented aer_vector() callback and MSI init/uninit hooks > - Updated Root Port SSID to 0x1150 to reflect the platform default > > Enabling MSI is required for proper PCIe Hotplug event signaling. This change > improves correctness and ensures QEMU Root Port behavior matches the behavior > of ASPEED hardware and downstream kernel expectations. > > Signed-off-by: Jamin Lin > --- > hw/pci-host/aspeed_pcie.c | 40 ++++++++++++++++++++++++++++++++++++++- > 1 file changed, 39 insertions(+), 1 deletion(-) It seems that we should queue this patch for QEMU 10.2. If so, could you provide a fixes tag please ? Thanks, C. > > diff --git a/hw/pci-host/aspeed_pcie.c b/hw/pci-host/aspeed_pcie.c > index f7593444fc..1fc2c61772 100644 > --- a/hw/pci-host/aspeed_pcie.c > +++ b/hw/pci-host/aspeed_pcie.c > @@ -68,6 +68,38 @@ static const TypeInfo aspeed_pcie_root_device_info = { > * PCIe Root Port > */ > > +#define ASPEED_PCIE_ROOT_PORT_MSI_OFFSET 0x50 > +#define ASPEED_PCIE_ROOT_PORT_MSI_NR_VECTOR 1 > +#define ASPEED_PCIE_ROOT_PORT_SSVID_OFFSET 0xC0 > +#define ASPEED_PCIE_ROOT_PORT_EXP_OFFSET 0x80 > +#define ASPEED_PCIE_ROOT_PORT_AER_OFFSET 0x100 > + > +static uint8_t aspeed_pcie_root_port_aer_vector(const PCIDevice *d) > +{ > + return 0; > +} > + > +static int aspeed_pcie_root_port_interrupts_init(PCIDevice *d, Error **errp) > +{ > + int rc; > + > + rc = msi_init(d, ASPEED_PCIE_ROOT_PORT_MSI_OFFSET, > + ASPEED_PCIE_ROOT_PORT_MSI_NR_VECTOR, > + PCI_MSI_FLAGS_MASKBIT & PCI_MSI_FLAGS_64BIT, > + PCI_MSI_FLAGS_MASKBIT & PCI_MSI_FLAGS_MASKBIT, > + errp); > + if (rc < 0) { > + assert(rc == -ENOTSUP); > + } > + > + return rc; > +} > + > +static void aspeed_pcie_root_port_interrupts_uninit(PCIDevice *d) > +{ > + msi_uninit(d); > +} > + > static void aspeed_pcie_root_port_class_init(ObjectClass *klass, > const void *data) > { > @@ -80,7 +112,13 @@ static void aspeed_pcie_root_port_class_init(ObjectClass *klass, > k->device_id = 0x1150; > dc->user_creatable = true; > > - rpc->aer_offset = 0x100; > + rpc->aer_vector = aspeed_pcie_root_port_aer_vector; > + rpc->interrupts_init = aspeed_pcie_root_port_interrupts_init; > + rpc->interrupts_uninit = aspeed_pcie_root_port_interrupts_uninit; > + rpc->exp_offset = ASPEED_PCIE_ROOT_PORT_EXP_OFFSET; > + rpc->aer_offset = ASPEED_PCIE_ROOT_PORT_AER_OFFSET; > + rpc->ssvid_offset = ASPEED_PCIE_ROOT_PORT_SSVID_OFFSET; > + rpc->ssid = 0x1150; > } > > static const TypeInfo aspeed_pcie_root_port_info = {