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[83.57.174.129]) by smtp.gmail.com with ESMTPSA id o19sm20317772wmh.27.2019.10.23.03.47.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 23 Oct 2019 03:47:50 -0700 (PDT) Subject: Re: [Qemu-devel] [PATCH] pci_bridge: fix a typo in comment To: maozy , qemu-devel@nongnu.org References: <20181108122102.9915-1-maozhongyi@cmss.chinamobile.com> <1898dc23-c512-88bd-cb73-5a2cffccd176@redhat.com> <7f3e7954-3574-9f44-7710-4a488c1d0fe2@cmss.chinamobile.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Wed, 23 Oct 2019 12:47:49 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.1.1 MIME-Version: 1.0 In-Reply-To: <7f3e7954-3574-9f44-7710-4a488c1d0fe2@cmss.chinamobile.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: QEMU Trivial , mst@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 10/23/19 5:32 AM, maozy wrote: > ping... I'm not sure qemu-trivial@ received this one because the email address=20 looked odd (now fixed). >=20 > On 11/8/18 9:12 PM, Philippe Mathieu-Daud=C3=A9 wrote: >> Cc'ing qemu-trivial@ >> >> On 8/11/18 13:21, Mao Zhongyi wrote: >>> Signed-off-by: Mao Zhongyi >> >> Reviewed-by: Philippe Mathieu-Daud=C3=A9 >> >>> --- >>> =C2=A0 hw/pci/pci_bridge.c | 2 +- >>> =C2=A0 1 file changed, 1 insertion(+), 1 deletion(-) >>> >>> diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c >>> index ee9dff2d3a..da8daa3ff2 100644 >>> --- a/hw/pci/pci_bridge.c >>> +++ b/hw/pci/pci_bridge.c >>> @@ -310,7 +310,7 @@ void pci_bridge_reset(DeviceState *qdev) >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * the default values for base/li= mit registers aren't specified >>> -=C2=A0=C2=A0=C2=A0=C2=A0 * in the PCI-to-PCI-bridge spec. So we don'= t thouch them here. >>> +=C2=A0=C2=A0=C2=A0=C2=A0 * in the PCI-to-PCI-bridge spec. So we don'= t touch them here. >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * Each implementation can overri= de it. >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * typical implementation does >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * zero base/limit registers or >>> >> >=20 >=20