From: Julia Suvorova <jusual@mail.ru>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-devel <qemu-devel@nongnu.org>,
"Stefan Hajnoczi" <stefanha@gmail.com>,
"Joel Stanley" <joel@jms.id.au>,
"Jim Mussared" <jim@groklearning.com>,
"Steffen Görtz" <mail@steffen-goertz.de>
Subject: Re: [Qemu-devel] [PATCH v2] nvic: Change NVIC to support ARMv6-M
Date: Fri, 20 Jul 2018 11:09:10 +0300 [thread overview]
Message-ID: <f6970c0f-d9d5-1d5d-7d6e-3e457f034bf2@mail.ru> (raw)
In-Reply-To: <CAFEAcA8_2hM0J38w0h0jfVMvLMceHnxgKKYeMcY-SO_Ywk0QpA@mail.gmail.com>
On 19.07.2018 19:25, Peter Maydell wrote:
> On 19 July 2018 at 13:16, Julia Suvorova <jusual@mail.ru> wrote:
>> The differences from ARMv7-M NVIC are:
>> * ARMv6-M only supports up to 32 external interrupts
>> (configurable feature already). The ICTR is reserved.
>> * Active Bit Register is reserved.
>> * ARMv6-M supports 4 priority levels against 256 in ARMv7-M.
>>
>> Signed-off-by: Julia Suvorova <jusual@mail.ru>
>> ---
>> v2:
>> * Added num_prio_bits field
>> * AIRCR.PRIGROUP is set as RAZ/WI for Baseline
>
> Applied to target-arm.for-3.1, thanks.
It seems like you applied the first version of this patch.
Can you check this, please?
Best regards, Julia Suvorova.
next prev parent reply other threads:[~2018-07-20 8:09 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-19 12:16 [Qemu-devel] [PATCH v2] nvic: Change NVIC to support ARMv6-M Julia Suvorova
2018-07-19 16:25 ` Peter Maydell
2018-07-20 8:09 ` Julia Suvorova [this message]
2018-07-20 9:07 ` Peter Maydell
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