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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id n7sm18294205edb.34.2020.12.08.11.12.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 08 Dec 2020 11:12:32 -0800 (PST) Subject: Re: [PATCH-for-5.2?] target/mips/translate: Check R6 reserved encoding for Load Linked Word To: "Maciej W. Rozycki" References: <20201124134557.569388-1-f4bug@amsat.org> <5bcade19-de8c-8521-f77c-599e3c9d40a0@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Tue, 8 Dec 2020 20:12:31 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.4.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::532; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-x532.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Richard Henderson , "qemu-devel@nongnu.org Developers" , Aurelien Jarno Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 12/8/20 7:43 PM, Maciej W. Rozycki wrote: > On Tue, 8 Dec 2020, Philippe Mathieu-Daudé wrote: > >> Duh I hit that again, read the patch again, looks correct. I guess >> I got confused myself reviewing the offending patch... >> So I'm applying this patch to mips-next queue, using >> Fixes: d9224450208 ("target-mips: Tighten ISA level checks") > > What's wrong with current code? What I can see is: > > case OPC_LL: /* Load and stores */ > check_insn(ctx, ISA_MIPS2); > if (ctx->insn_flags & INSN_R5900) { > check_insn_opc_user_only(ctx, INSN_R5900); > } > /* Fallthrough */ > case OPC_LWL: > case OPC_LWR: > check_insn_opc_removed(ctx, ISA_MIPS32R6); > /* Fallthrough */ > case OPC_LB: > case OPC_LH: > case OPC_LW: > case OPC_LWPC: > case OPC_LBU: > case OPC_LHU: > gen_ld(ctx, op, rt, rs, imm); > break; > > which looks absolutely right to me: LL is accepted with MIPS2--MIPS32R5 > (including R5900 in user emulation only), LWL/LWR are accepted with > MIPS1--MIPS32R5 and the remaining loads are accepted everywhere. What > else do you need? I am clearly bleary-eyed... Sorry. Patch dropped.