From: "Cédric Le Goater" <clg@kaod.org>
To: Jamin Lin <jamin_lin@aspeedtech.com>,
Peter Maydell <peter.maydell@linaro.org>,
Steven Lee <steven_lee@aspeedtech.com>,
Troy Lee <leetroy@gmail.com>,
Andrew Jeffery <andrew@codeconstruct.com.au>,
Joel Stanley <joel@jms.id.au>,
"open list:All patches CC here" <qemu-devel@nongnu.org>,
"open list:ASPEED BMCs" <qemu-arm@nongnu.org>
Cc: troy_lee@aspeedtech.com
Subject: Re: [PATCH v5 00/29] Support AST2700 A1
Date: Thu, 6 Mar 2025 16:27:10 +0100 [thread overview]
Message-ID: <f6bc0f9c-e208-4a07-b2a0-02f0a23b220e@kaod.org> (raw)
In-Reply-To: <20250306103846.429221-1-jamin_lin@aspeedtech.com>
Jamin,
On 3/6/25 11:38, Jamin Lin wrote:
> v1:
> 1. Refactor INTC model to support both INTC0 and INTC1.
> 2. Support AST2700 A1.
> 3. Create ast2700a0-evb machine.
>
> v2:
> To streamline the review process, split the following patch series into
> three parts.
> https://patchwork.kernel.org/project/qemu-devel/cover/20250121070424.2465942-1-jamin_lin@aspeedtech.com/
> This patch series focuses on cleaning up the INTC model to
> facilitate future support for the INTC_IO model.
>
> v3:
> 1. Update and add functional test for AST2700
> 2. Add AST2700 INTC design guidance and its block diagram.
> 3. Retaining the INTC naming and introducing a new INTCIO model to support the AST2700 A1.
> 4. Create ast2700a1-evb machine and rename ast2700a0-evb machine
> 5. Fix silicon revision issue and support AST2700 A1.
>
> v4:
> 1. rework functional test for AST2700
> 2. the initial machine "ast2700-evb" is aliased to "ast2700a0-evb.
> 3. intc: Reduce regs array size by adding a register sub-region
> 4. intc: split patch for Support setting different register sizes
> 5. update ast2700a1-evb machine parent to TYPE_ASPEED_MACHINE
>
> v5:
> 1. Rename status_addr and addr to status_reg and reg for clarity
> 2. Introduce dynamic allocation for regs array
> 3. Sort the memmap table by mapping address
> 4. ast27x0.c split patch for Support two levels of INTC controllers for AST2700 A1
> 5. tests/functional/aspped split patch for Introduce start_ast2700_test API
> 6. keep variable naming for reviewer suggestion.
> 7. Add reviewer suggestion and split patch to make more readable.
>
> With the patch applied, QEMU now supports two machines for running AST2700 SoCs:
> ast2700a0-evb: Designed for AST2700 A0
> ast2700a1-evb: Designed for AST2700 A1
>
> Test information
> 1. QEMU version: https://github.com/qemu/qemu/commit/50d38b8921837827ea397d4b20c8bc5efe186e53
> 2. ASPEED SDK v09.05 pre-built image
> https://github.com/AspeedTech-BMC/openbmc/releases/tag/v09.05
> ast2700-default-obmc.tar.gz (AST2700 A1)
> https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.05/ast2700-default-obmc.tar.gz
> ast2700-a0-default-obmc.tar.gz (AST2700 A0)
> https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.05/ast2700-a0-default-obmc.tar.gz
>
> This patch series depends on the following patch series:
> https://patchwork.kernel.org/project/qemu-devel/cover/20250303073547.1145080-1-jamin_lin@aspeedtech.com/
> https://patchwork.kernel.org/project/qemu-devel/cover/20250225075622.305515-1-jamin_lin@aspeedtech.com/
>
> Jamin Lin (29):
> hw/intc/aspeed: Support setting different memory size
> hw/intc/aspeed: Rename status_addr and addr to status_reg and reg for
> clarity
> hw/intc/aspeed: Introduce dynamic allocation for regs array
> hw/intc/aspeed: Support setting different register size
> hw/intc/aspeed: Reduce regs array size by adding a register sub-region
> hw/intc/aspeed: Introduce helper functions for enable and status
> registers
> hw/intc/aspeed: Add object type name to trace events for better
> debugging
> hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0
> hw/arm/aspeed_ast27x0: Sort the IRQ table by IRQ number
> hw/intc/aspeed: Support different memory region ops
> hw/intc/aspeed: Rename num_ints to num_inpins for clarity
> hw/intc/aspeed: Add support for multiple output pins in INTC
> hw/intc/aspeed: Refactor INTC to support separate input and output pin
> indices
> hw/intc/aspeed: Introduce AspeedINTCIRQ structure to save the irq
> index and register address
> hw/intc/aspeed: Introduce IRQ handler function to reduce code
> duplication
> hw/intc/aspeed: Add Support for Multi-Output IRQ Handling
> hw/intc/aspeed: Add Support for AST2700 INTCIO Controller
> hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon
> Revisions
> hw/arm/aspeed_ast27x0.c Support AST2700 A1 GIC Interrupt Mapping
> hw/arm/aspeed_ast27x0: Define an Array of AspeedINTCState with Two
> Instances
> hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for
> AST2700 A1
> hw/arm/aspeed_ast27x0: Add SoC Support for AST2700 A1
> hw/arm/aspeed: Add Machine Support for AST2700 A1
> hw/arm/aspeed_ast27x0: Sort the memmap table by mapping address
> tests/functional/aspeed: Introduce start_ast2700_test API
> tests/functional/aspeed: Update temperature hwmon path
> tests/functional/aspeed: Update test ASPEED SDK v09.05
> tests/functional/aspeed: Add test case for AST2700 A1
> docs/specs: Add aspeed-intc
>
> docs/specs/aspeed-intc.rst | 136 +++++
> docs/specs/index.rst | 1 +
> include/hw/arm/aspeed_soc.h | 3 +-
> include/hw/intc/aspeed_intc.h | 36 +-
> include/hw/misc/aspeed_scu.h | 2 +
> hw/arm/aspeed.c | 33 +-
> hw/arm/aspeed_ast27x0.c | 329 ++++++++----
> hw/intc/aspeed_intc.c | 667 ++++++++++++++++++------
> hw/misc/aspeed_scu.c | 2 +
> hw/intc/trace-events | 25 +-
> tests/functional/test_aarch64_aspeed.py | 47 +-
> 11 files changed, 978 insertions(+), 303 deletions(-)
> create mode 100644 docs/specs/aspeed-intc.rst
>
Patches 3-5 need some care. The rest looks OK.
Thanks,
C.
prev parent reply other threads:[~2025-03-06 15:27 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-06 10:38 [PATCH v5 00/29] Support AST2700 A1 Jamin Lin via
2025-03-06 10:38 ` [PATCH v5 01/29] hw/intc/aspeed: Support setting different memory size Jamin Lin via
2025-03-06 15:04 ` Cédric Le Goater
2025-03-06 10:38 ` [PATCH v5 02/29] hw/intc/aspeed: Rename status_addr and addr to status_reg and reg for clarity Jamin Lin via
2025-03-06 15:04 ` Cédric Le Goater
2025-03-06 10:38 ` [PATCH v5 03/29] hw/intc/aspeed: Introduce dynamic allocation for regs array Jamin Lin via
2025-03-06 15:22 ` Cédric Le Goater
2025-03-07 2:23 ` Jamin Lin
2025-03-06 10:38 ` [PATCH v5 04/29] hw/intc/aspeed: Support setting different register size Jamin Lin via
2025-03-06 15:24 ` Cédric Le Goater
2025-03-07 2:43 ` Jamin Lin
2025-03-06 10:38 ` [PATCH v5 05/29] hw/intc/aspeed: Reduce regs array size by adding a register sub-region Jamin Lin via
2025-03-06 10:38 ` [PATCH v5 06/29] hw/intc/aspeed: Introduce helper functions for enable and status registers Jamin Lin via
2025-03-06 10:38 ` [PATCH v5 07/29] hw/intc/aspeed: Add object type name to trace events for better debugging Jamin Lin via
2025-03-06 10:38 ` [PATCH v5 08/29] hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0 Jamin Lin via
2025-03-06 15:08 ` Cédric Le Goater
2025-03-06 10:38 ` [PATCH v5 09/29] hw/arm/aspeed_ast27x0: Sort the IRQ table by IRQ number Jamin Lin via
2025-03-06 10:38 ` [PATCH v5 10/29] hw/intc/aspeed: Support different memory region ops Jamin Lin via
2025-03-06 10:38 ` [PATCH v5 11/29] hw/intc/aspeed: Rename num_ints to num_inpins for clarity Jamin Lin via
2025-03-06 10:38 ` [PATCH v5 12/29] hw/intc/aspeed: Add support for multiple output pins in INTC Jamin Lin via
2025-03-06 10:38 ` [PATCH v5 13/29] hw/intc/aspeed: Refactor INTC to support separate input and output pin indices Jamin Lin via
2025-03-06 10:38 ` [PATCH v5 14/29] hw/intc/aspeed: Introduce AspeedINTCIRQ structure to save the irq index and register address Jamin Lin via
2025-03-06 15:10 ` Cédric Le Goater
2025-03-06 10:38 ` [PATCH v5 15/29] hw/intc/aspeed: Introduce IRQ handler function to reduce code duplication Jamin Lin via
2025-03-06 10:38 ` [PATCH v5 16/29] hw/intc/aspeed: Add Support for Multi-Output IRQ Handling Jamin Lin via
2025-03-06 15:10 ` Cédric Le Goater
2025-03-06 10:38 ` [PATCH v5 17/29] hw/intc/aspeed: Add Support for AST2700 INTCIO Controller Jamin Lin via
2025-03-06 10:38 ` [PATCH v5 18/29] hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon Revisions Jamin Lin via
2025-03-06 10:38 ` [PATCH v5 19/29] hw/arm/aspeed_ast27x0.c Support AST2700 A1 GIC Interrupt Mapping Jamin Lin via
2025-03-06 10:38 ` [PATCH v5 20/29] hw/arm/aspeed_ast27x0: Define an Array of AspeedINTCState with Two Instances Jamin Lin via
2025-03-06 15:11 ` Cédric Le Goater
2025-03-06 10:38 ` [PATCH v5 21/29] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1 Jamin Lin via
2025-03-06 15:12 ` Cédric Le Goater
2025-03-06 10:38 ` [PATCH v5 22/29] hw/arm/aspeed_ast27x0: Add SoC Support " Jamin Lin via
2025-03-06 10:38 ` [PATCH v5 23/29] hw/arm/aspeed: Add Machine " Jamin Lin via
2025-03-06 15:12 ` Cédric Le Goater
2025-03-06 10:38 ` [PATCH v5 24/29] hw/arm/aspeed_ast27x0: Sort the memmap table by mapping address Jamin Lin via
2025-03-06 15:12 ` Cédric Le Goater
2025-03-06 10:38 ` [PATCH v5 25/29] tests/functional/aspeed: Introduce start_ast2700_test API Jamin Lin via
2025-03-06 15:13 ` Cédric Le Goater
2025-03-06 10:38 ` [PATCH v5 26/29] tests/functional/aspeed: Update temperature hwmon path Jamin Lin via
2025-03-06 15:13 ` Cédric Le Goater
2025-03-06 10:38 ` [PATCH v5 27/29] tests/functional/aspeed: Update test ASPEED SDK v09.05 Jamin Lin via
2025-03-06 10:38 ` [PATCH v5 28/29] tests/functional/aspeed: Add test case for AST2700 A1 Jamin Lin via
2025-03-06 10:38 ` [PATCH v5 29/29] docs/specs: Add aspeed-intc Jamin Lin via
2025-03-06 15:27 ` Cédric Le Goater [this message]
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