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From: Richard Henderson <richard.henderson@linaro.org>
To: "Víctor Colombo" <victor.colombo@eldorado.org.br>,
	qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Cc: clg@kaod.org, danielhb413@gmail.com, david@gibson.dropbear.id.au,
	groug@kaod.org
Subject: Re: [PATCH RESEND 04/10] target/ppc: Move mffsce to decodetree
Date: Tue, 17 May 2022 11:49:29 -0700	[thread overview]
Message-ID: <f6d33484-1a5c-9b1c-fa15-5ef557571601@linaro.org> (raw)
In-Reply-To: <20220517164744.58131-5-victor.colombo@eldorado.org.br>

On 5/17/22 09:47, Víctor Colombo wrote:
> -static void do_mffsc(int rt, uint64_t set_mask)
> +static void do_mffsc(int rt, TCGv_i64 t1, uint64_t set_mask,
> +                     uint64_t clear_mask, uint32_t fpscr_mask)
>   {
>       TCGv_i64 fpscr;
>   
> @@ -618,6 +619,12 @@ static void do_mffsc(int rt, uint64_t set_mask)
>       tcg_gen_andi_i64(fpscr, fpscr, set_mask);
>       set_fpr(rt, fpscr);
>   
> +    if (fpscr_mask) {
> +        tcg_gen_andi_i64(fpscr, fpscr, clear_mask);

The naming doesn't seem right for clear_mask.  I would expect clear_mask to contain the 
bits that we want to remove, and the computation to be

    fpscr &= ~clear_mask

> +        tcg_gen_or_i64(fpscr, fpscr, t1);

Can we get a better name than t1?  Also, I think perhaps NULL would be better for when we 
do not wish to include this.  I suppose tcg_constant_i64(0) is *probably* already in the 
constant hash table, but why look it up at all?

> +        gen_helper_store_fpscr(cpu_env, fpscr, tcg_constant_i32(fpscr_mask));

Given than everything in here is fpscr related, perhaps "store_mask" is a better name?

Also, this is the second time we're modifying the new do_mffsc function.  Does it actually 
make more sense to reverse the order of these patches so that MFFSCRN comes first, as that 
is the one that takes the most complex form of do_mffsc.

Alternately, does it really make sense to try to do everything in one function, with 4 
extra parameters that turn out to be very specific to single instructions?  E.g. the t1 
parameter would probably be better implemented with a deposit of the RN field, rather than 
separate ANDs and OR.


r~


  reply	other threads:[~2022-05-17 19:02 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-17 16:47 [PATCH RESEND 00/10] BCDA and mffscdrn implementations Víctor Colombo
2022-05-17 16:47 ` [PATCH RESEND 01/10] target/ppc: Fix insn32.decode style issues Víctor Colombo
2022-05-17 18:25   ` Richard Henderson
2022-05-17 16:47 ` [PATCH RESEND 02/10] target/ppc: Move mffs[.] to decodetree Víctor Colombo
2022-05-17 18:30   ` Richard Henderson
2022-05-17 16:47 ` [PATCH RESEND 03/10] target/ppc: Move mffsl " Víctor Colombo
2022-05-17 18:30   ` Richard Henderson
2022-05-17 18:45   ` Richard Henderson
2022-05-17 16:47 ` [PATCH RESEND 04/10] target/ppc: Move mffsce " Víctor Colombo
2022-05-17 18:49   ` Richard Henderson [this message]
2022-05-17 16:47 ` [PATCH RESEND 05/10] target/ppc: Move mffscrn[i] " Víctor Colombo
2022-05-17 16:47 ` [PATCH RESEND 06/10] target/ppc: Implement mffscdrn[i] instructions Víctor Colombo
2022-05-17 18:52   ` Richard Henderson
2022-05-17 16:47 ` [PATCH RESEND 07/10] target/ppc: Add flag for ISA v2.06 BCDA instructions Víctor Colombo
2022-05-17 18:54   ` Richard Henderson
2022-05-17 16:47 ` [PATCH RESEND 08/10] target/ppc: implement addg6s Víctor Colombo
2022-05-17 19:05   ` Richard Henderson
2022-05-17 16:47 ` [PATCH RESEND 09/10] target/ppc: implement cbcdtd Víctor Colombo
2022-05-17 19:10   ` Richard Henderson
2022-05-17 16:47 ` [PATCH RESEND 10/10] target/ppc: implement cdtbcd Víctor Colombo
2022-05-17 19:12   ` Richard Henderson

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