From: David Hildenbrand <david@redhat.com>
To: Richard Henderson <rth@twiddle.net>, qemu-devel@nongnu.org
Cc: thuth@redhat.com, aurelien@aurel32.net
Subject: Re: [Qemu-devel] [PATCH v3 15/18] target/s390x: Implement SRSTU
Date: Tue, 20 Jun 2017 10:27:11 +0200 [thread overview]
Message-ID: <f6f19088-0284-2f22-c6fb-0739efe35ee1@redhat.com> (raw)
In-Reply-To: <169e898c-98f6-a6d6-7045-1b2606469fe4@redhat.com>
> Apart from special wrapping conditions, looks good to me!
>
> (will scan the PoP how wrapping is to be handled in general during an
> instruction. Some (like mvcos) mention it explicitly, others don't)
>
Answering my own questions:
1. We always have to wrap addresses that we generate except in some
special cases:
(PoP page 3-7)
"
The CPU performs address generation when it forms
an operand or instruction address or when it gener-
ates the address of a table entry from the appropriate
table origin and index. It also performs address gen-
eration when it increments an address to access suc-
cessive bytes of a field.
When, during the generation of the address, an
address is obtained that exceeds the value allowed
[...] one of the following two actions is taken:
1. The carry out of the high-order bit position of the
address is ignored. This handling of an address
of excessive size is called wraparound.
2. An interruption condition is recognized.
[...]
Addresses generated by the CPU that may be virtual
addresses always wrap."
... reading the following table, interrupts seem to get generated only
for some iplicit DAT translations/AR-mode tables and authority tables,
and only when Real or Absolute addresses are to be used.
So wrapping all addresses is done in general when working with virtual
addresses, whenever we generate an address.
2. We must not overwrite bit 0-31 in 24/31 bit mode:
(PoP page 3-6)
Unless specifically stated to the contrary, the follow-
ing definition applies in this publication: whenever the
machine generates and provides to the program a
24-bit or 31-bit address, the address is made avail-
able (placed in storage or loaded into a general regis-
ter) by being imbedded in a 32-bit field, with the
leftmost eight bits or one bit in the field, respectively,
set to zeros. When the address is loaded into a gen-
eral register, bits 0-31 of the register remain
unchanged.
--
Thanks,
David
next prev parent reply other threads:[~2017-06-20 8:27 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-20 0:03 [Qemu-devel] [PATCH v3 00/18] target/s390x improvements Richard Henderson
2017-06-20 0:03 ` [Qemu-devel] [PATCH v3 01/18] target/s390x: Map existing FAC_* names to S390_FEAT_* names Richard Henderson
2017-06-23 10:58 ` Aurelien Jarno
2017-06-20 0:03 ` [Qemu-devel] [PATCH v3 02/18] target/s390x: change PSW_SHIFT_KEY Richard Henderson
2017-06-23 10:59 ` Aurelien Jarno
2017-06-20 0:03 ` [Qemu-devel] [PATCH v3 03/18] target/s390x: implement mvcos instruction Richard Henderson
2017-06-20 0:03 ` [Qemu-devel] [PATCH v3 04/18] target/s390x: Implement CSST Richard Henderson
2017-06-20 0:03 ` [Qemu-devel] [PATCH v3 05/18] target/s390x: Mark FPSEH facility as available Richard Henderson
2017-06-23 10:59 ` Aurelien Jarno
2017-06-20 0:03 ` [Qemu-devel] [PATCH v3 06/18] target/s390x: Implement load-on-condition-2 insns Richard Henderson
2017-06-23 11:00 ` Aurelien Jarno
2017-06-20 0:03 ` [Qemu-devel] [PATCH v3 08/18] target/s390x: Mark STFLE_53 facility as available Richard Henderson
2017-06-23 11:01 ` Aurelien Jarno
2017-06-20 0:03 ` [Qemu-devel] [PATCH v3 10/18] target/s390x: Implement processor-assist insn Richard Henderson
2017-06-23 11:01 ` Aurelien Jarno
2017-06-20 0:03 ` [Qemu-devel] [PATCH v3 11/18] target/s390x: Mark STFLE_49 facility as available Richard Henderson
2017-06-23 11:01 ` Aurelien Jarno
2017-06-20 0:03 ` [Qemu-devel] [PATCH v3 12/18] target/s390x: Finish implementing ETF2-ENH Richard Henderson
2017-06-23 11:02 ` Aurelien Jarno
2017-06-20 0:04 ` [Qemu-devel] [PATCH v3 13/18] target/s390x: Implement CONVERT UNICODE insns Richard Henderson
2017-06-23 15:52 ` Aurelien Jarno
2017-06-20 0:04 ` [Qemu-devel] [PATCH v3 14/18] target/s390x: Tidy SRST Richard Henderson
2017-06-20 7:33 ` David Hildenbrand
2017-06-23 15:52 ` Aurelien Jarno
2017-06-20 0:04 ` [Qemu-devel] [PATCH v3 15/18] target/s390x: Implement SRSTU Richard Henderson
2017-06-20 8:12 ` David Hildenbrand
2017-06-20 8:27 ` David Hildenbrand [this message]
2017-06-20 17:21 ` Richard Henderson
2017-06-23 15:52 ` Aurelien Jarno
2017-06-20 0:04 ` [Qemu-devel] [PATCH v3 16/18] target/s390x: Implement TRTR Richard Henderson
2017-06-23 15:53 ` Aurelien Jarno
2017-06-20 0:04 ` [Qemu-devel] [PATCH v3 17/18] target/s390x: Mark ETF3 and ETF3_ENH facilities as available Richard Henderson
2017-06-23 15:53 ` Aurelien Jarno
2017-06-20 0:04 ` [Qemu-devel] [PATCH v3 18/18] target/s390x: Clean up TB flag bits Richard Henderson
2017-06-20 3:16 ` Philippe Mathieu-Daudé
2017-06-23 15:53 ` Aurelien Jarno
[not found] ` <20170620000405.3391-8-rth@twiddle.net>
2017-06-23 11:01 ` [Qemu-devel] [PATCH v3 07/18] target/s390x: Implement load-and-zero-rightmost-byte insns Aurelien Jarno
[not found] ` <20170620000405.3391-10-rth@twiddle.net>
2017-06-23 11:01 ` [Qemu-devel] [PATCH v3 09/18] target/s390x: Implement execution-hint insns Aurelien Jarno
2017-06-23 16:05 ` [Qemu-devel] [PATCH v3 00/18] target/s390x improvements Aurelien Jarno
2017-06-27 15:54 ` David Hildenbrand
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