* [Qemu-devel] [PATCH v3 01/18] target/s390x: Map existing FAC_* names to S390_FEAT_* names
2017-06-20 0:03 [Qemu-devel] [PATCH v3 00/18] target/s390x improvements Richard Henderson
@ 2017-06-20 0:03 ` Richard Henderson
2017-06-23 10:58 ` Aurelien Jarno
2017-06-20 0:03 ` [Qemu-devel] [PATCH v3 02/18] target/s390x: change PSW_SHIFT_KEY Richard Henderson
` (17 subsequent siblings)
18 siblings, 1 reply; 40+ messages in thread
From: Richard Henderson @ 2017-06-20 0:03 UTC (permalink / raw)
To: qemu-devel; +Cc: thuth, aurelien
The FAC_ names were placeholders prior to the introduction
of the current facility modeling.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target/s390x/translate.c | 59 ++++++++++++++++++++++++------------------------
1 file changed, 29 insertions(+), 30 deletions(-)
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 8c055b7..af18ffb 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -1178,39 +1178,10 @@ typedef enum {
EXIT_NORETURN,
} ExitStatus;
-typedef enum DisasFacility {
- FAC_Z, /* zarch (default) */
- FAC_CASS, /* compare and swap and store */
- FAC_CASS2, /* compare and swap and store 2*/
- FAC_DFP, /* decimal floating point */
- FAC_DFPR, /* decimal floating point rounding */
- FAC_DO, /* distinct operands */
- FAC_EE, /* execute extensions */
- FAC_EI, /* extended immediate */
- FAC_FPE, /* floating point extension */
- FAC_FPSSH, /* floating point support sign handling */
- FAC_FPRGR, /* FPR-GR transfer */
- FAC_GIE, /* general instructions extension */
- FAC_HFP_MA, /* HFP multiply-and-add/subtract */
- FAC_HW, /* high-word */
- FAC_IEEEE_SIM, /* IEEE exception sumilation */
- FAC_MIE, /* miscellaneous-instruction-extensions */
- FAC_LAT, /* load-and-trap */
- FAC_LOC, /* load/store on condition */
- FAC_LD, /* long displacement */
- FAC_PC, /* population count */
- FAC_SCF, /* store clock fast */
- FAC_SFLE, /* store facility list extended */
- FAC_ILA, /* interlocked access facility 1 */
- FAC_LPP, /* load-program-parameter */
- FAC_DAT_ENH, /* DAT-enhancement */
- FAC_E2, /* extended-translation facility 2 */
-} DisasFacility;
-
struct DisasInsn {
unsigned opc:16;
DisasFormat fmt:8;
- DisasFacility fac:8;
+ unsigned fac:8;
unsigned spec:8;
const char *name;
@@ -5413,6 +5384,34 @@ enum DisasInsnEnum {
#define SPEC_prep_0 0
#define SPEC_wout_0 0
+/* Give smaller names to the various facilities. */
+#define FAC_Z S390_FEAT_ZARCH
+#define FAC_CASS S390_FEAT_COMPARE_AND_SWAP_AND_STORE
+#define FAC_CASS2 S390_FEAT_COMPARE_AND_SWAP_AND_STORE_2
+#define FAC_DFP S390_FEAT_DFP
+#define FAC_DFPR S390_FEAT_FLOATING_POINT_SUPPPORT_ENH /* DFP-rounding */
+#define FAC_DO S390_FEAT_STFLE_45 /* distinct-operands */
+#define FAC_EE S390_FEAT_EXECUTE_EXT
+#define FAC_EI S390_FEAT_EXTENDED_IMMEDIATE
+#define FAC_FPE S390_FEAT_FLOATING_POINT_EXT
+#define FAC_FPSSH S390_FEAT_FLOATING_POINT_SUPPPORT_ENH /* FPS-sign-handling */
+#define FAC_FPRGR S390_FEAT_FLOATING_POINT_SUPPPORT_ENH /* FPR-GR-transfer */
+#define FAC_GIE S390_FEAT_GENERAL_INSTRUCTIONS_EXT
+#define FAC_HFP_MA S390_FEAT_HFP_MADDSUB
+#define FAC_HW S390_FEAT_STFLE_45 /* high-word */
+#define FAC_IEEEE_SIM S390_FEAT_FLOATING_POINT_SUPPPORT_ENH /* IEEE-exception-simulation */
+#define FAC_MIE S390_FEAT_STFLE_49 /* misc-instruction-extensions */
+#define FAC_LAT S390_FEAT_STFLE_49 /* load-and-trap */
+#define FAC_LOC S390_FEAT_STFLE_45 /* load/store on condition 1 */
+#define FAC_LD S390_FEAT_LONG_DISPLACEMENT
+#define FAC_PC S390_FEAT_STFLE_45 /* population count */
+#define FAC_SCF S390_FEAT_STORE_CLOCK_FAST
+#define FAC_SFLE S390_FEAT_STFLE
+#define FAC_ILA S390_FEAT_STFLE_45 /* interlocked-access-facility 1 */
+#define FAC_LPP S390_FEAT_SET_PROGRAM_PARAMETERS /* load-program-parameter */
+#define FAC_DAT_ENH S390_FEAT_DAT_ENH
+#define FAC_E2 S390_FEAT_EXTENDED_TRANSLATION_2
+
static const DisasInsn insn_info[] = {
#include "insn-data.def"
};
--
2.9.4
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Qemu-devel] [PATCH v3 02/18] target/s390x: change PSW_SHIFT_KEY
2017-06-20 0:03 [Qemu-devel] [PATCH v3 00/18] target/s390x improvements Richard Henderson
2017-06-20 0:03 ` [Qemu-devel] [PATCH v3 01/18] target/s390x: Map existing FAC_* names to S390_FEAT_* names Richard Henderson
@ 2017-06-20 0:03 ` Richard Henderson
2017-06-23 10:59 ` Aurelien Jarno
2017-06-20 0:03 ` [Qemu-devel] [PATCH v3 03/18] target/s390x: implement mvcos instruction Richard Henderson
` (16 subsequent siblings)
18 siblings, 1 reply; 40+ messages in thread
From: Richard Henderson @ 2017-06-20 0:03 UTC (permalink / raw)
To: qemu-devel; +Cc: thuth, aurelien, David Hildenbrand
From: David Hildenbrand <david@redhat.com>
Such shifts are usually used to easily extract the PSW KEY from the PSW
mask, so let's avoid the confusing offset of 4.
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20170614133819.18480-2-david@redhat.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target/s390x/cpu.h | 2 +-
target/s390x/translate.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index a4028fb..532a4a0 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -315,7 +315,7 @@ void s390x_cpu_debug_excp_handler(CPUState *cs);
#define PSW_MASK_IO 0x0200000000000000ULL
#define PSW_MASK_EXT 0x0100000000000000ULL
#define PSW_MASK_KEY 0x00F0000000000000ULL
-#define PSW_SHIFT_KEY 56
+#define PSW_SHIFT_KEY 52
#define PSW_MASK_MCHECK 0x0004000000000000ULL
#define PSW_MASK_WAIT 0x0002000000000000ULL
#define PSW_MASK_PSTATE 0x0001000000000000ULL
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index af18ffb..204b52a 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -3751,7 +3751,7 @@ static ExitStatus op_spka(DisasContext *s, DisasOps *o)
{
check_privileged(s);
tcg_gen_shri_i64(o->in2, o->in2, 4);
- tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, PSW_SHIFT_KEY - 4, 4);
+ tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, PSW_SHIFT_KEY, 4);
return NO_EXIT;
}
--
2.9.4
^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [Qemu-devel] [PATCH v3 02/18] target/s390x: change PSW_SHIFT_KEY
2017-06-20 0:03 ` [Qemu-devel] [PATCH v3 02/18] target/s390x: change PSW_SHIFT_KEY Richard Henderson
@ 2017-06-23 10:59 ` Aurelien Jarno
0 siblings, 0 replies; 40+ messages in thread
From: Aurelien Jarno @ 2017-06-23 10:59 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, thuth, David Hildenbrand
On 2017-06-19 17:03, Richard Henderson wrote:
> From: David Hildenbrand <david@redhat.com>
>
> Such shifts are usually used to easily extract the PSW KEY from the PSW
> mask, so let's avoid the confusing offset of 4.
>
> Reviewed-by: Thomas Huth <thuth@redhat.com>
> Signed-off-by: David Hildenbrand <david@redhat.com>
> Message-Id: <20170614133819.18480-2-david@redhat.com>
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target/s390x/cpu.h | 2 +-
> target/s390x/translate.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 40+ messages in thread
* [Qemu-devel] [PATCH v3 03/18] target/s390x: implement mvcos instruction
2017-06-20 0:03 [Qemu-devel] [PATCH v3 00/18] target/s390x improvements Richard Henderson
2017-06-20 0:03 ` [Qemu-devel] [PATCH v3 01/18] target/s390x: Map existing FAC_* names to S390_FEAT_* names Richard Henderson
2017-06-20 0:03 ` [Qemu-devel] [PATCH v3 02/18] target/s390x: change PSW_SHIFT_KEY Richard Henderson
@ 2017-06-20 0:03 ` Richard Henderson
2017-06-20 0:03 ` [Qemu-devel] [PATCH v3 04/18] target/s390x: Implement CSST Richard Henderson
` (15 subsequent siblings)
18 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2017-06-20 0:03 UTC (permalink / raw)
To: qemu-devel; +Cc: thuth, aurelien, David Hildenbrand
From: David Hildenbrand <david@redhat.com>
This adds support for the MOVE WITH OPTIONAL SPECIFICATIONS (MVCOS)
instruction. Allow to enable it for the qemu cpu model using
qemu-system-s390x ... -cpu qemu,mvcos=on ...
This allows to boot linux kernel that uses it for uacccess.
We are missing (as for most other part) low address protection checks,
PSW key / storage key checks and support for AR-mode.
We fake an ADDRESSING exception when called from problem state (which
seems to rely on PSW key checks to be in place) and if AR-mode is used.
user mode will always see a PRIVILEDGED exception.
This patch is based on an original patch by Miroslav Benes (thanks!).
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20170614133819.18480-3-david@redhat.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target/s390x/cpu.h | 22 +++++-
target/s390x/cpu_models.c | 1 +
target/s390x/helper.h | 1 +
target/s390x/insn-data.def | 2 +
target/s390x/mem_helper.c | 181 +++++++++++++++++++++++++++++++++++++++++----
target/s390x/translate.c | 9 +++
6 files changed, 201 insertions(+), 15 deletions(-)
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 532a4a0..5b94ace 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -304,6 +304,7 @@ void s390x_cpu_debug_excp_handler(CPUState *cs);
#undef PSW_MASK_WAIT
#undef PSW_MASK_PSTATE
#undef PSW_MASK_ASC
+#undef PSW_SHIFT_ASC
#undef PSW_MASK_CC
#undef PSW_MASK_PM
#undef PSW_MASK_64
@@ -320,6 +321,7 @@ void s390x_cpu_debug_excp_handler(CPUState *cs);
#define PSW_MASK_WAIT 0x0002000000000000ULL
#define PSW_MASK_PSTATE 0x0001000000000000ULL
#define PSW_MASK_ASC 0x0000C00000000000ULL
+#define PSW_SHIFT_ASC 46
#define PSW_MASK_CC 0x0000300000000000ULL
#define PSW_MASK_PM 0x00000F0000000000ULL
#define PSW_MASK_64 0x0000000100000000ULL
@@ -336,6 +338,12 @@ void s390x_cpu_debug_excp_handler(CPUState *cs);
#define PSW_ASC_SECONDARY 0x0000800000000000ULL
#define PSW_ASC_HOME 0x0000C00000000000ULL
+/* the address space values shifted */
+#define AS_PRIMARY 0
+#define AS_ACCREG 1
+#define AS_SECONDARY 2
+#define AS_HOME 3
+
/* tb flags */
#define FLAG_MASK_PER (PSW_MASK_PER >> 32)
@@ -354,6 +362,7 @@ void s390x_cpu_debug_excp_handler(CPUState *cs);
/* Control register 0 bits */
#define CR0_LOWPROT 0x0000000010000000ULL
+#define CR0_SECONDARY 0x0000000004000000ULL
#define CR0_EDAT 0x0000000000800000ULL
/* MMU */
@@ -361,7 +370,18 @@ void s390x_cpu_debug_excp_handler(CPUState *cs);
#define MMU_SECONDARY_IDX 1
#define MMU_HOME_IDX 2
-static inline int cpu_mmu_index (CPUS390XState *env, bool ifetch)
+static inline bool psw_key_valid(CPUS390XState *env, uint8_t psw_key)
+{
+ uint16_t pkm = env->cregs[3] >> 16;
+
+ if (env->psw.mask & PSW_MASK_PSTATE) {
+ /* PSW key has range 0..15, it is valid if the bit is 1 in the PKM */
+ return pkm & (0x80 >> psw_key);
+ }
+ return true;
+}
+
+static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch)
{
switch (env->psw.mask & PSW_MASK_ASC) {
case PSW_ASC_PRIMARY:
diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c
index 478bcc6..c3a4ce6 100644
--- a/target/s390x/cpu_models.c
+++ b/target/s390x/cpu_models.c
@@ -682,6 +682,7 @@ static void add_qemu_cpu_model_features(S390FeatBitmap fbm)
S390_FEAT_LONG_DISPLACEMENT_FAST,
S390_FEAT_ETF2_ENH,
S390_FEAT_STORE_CLOCK_FAST,
+ S390_FEAT_MOVE_WITH_OPTIONAL_SPEC,
S390_FEAT_GENERAL_INSTRUCTIONS_EXT,
S390_FEAT_EXECUTE_EXT,
S390_FEAT_STFLE_45,
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 69249a5..b268367 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -105,6 +105,7 @@ DEF_HELPER_FLAGS_1(stfl, TCG_CALL_NO_RWG, void, env)
DEF_HELPER_2(stfle, i32, env, i64)
DEF_HELPER_FLAGS_2(lpq, TCG_CALL_NO_WG, i64, env, i64)
DEF_HELPER_FLAGS_4(stpq, TCG_CALL_NO_WG, void, env, i64, i64, i64)
+DEF_HELPER_4(mvcos, i32, env, i64, i64, i64)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index d089707..aa4c5b2 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -590,6 +590,8 @@
C(0xb254, MVPG, RRE, Z, r1_o, r2_o, 0, 0, mvpg, 0)
/* MOVE STRING */
C(0xb255, MVST, RRE, Z, r1_o, r2_o, 0, 0, mvst, 0)
+/* MOVE WITH OPTIONAL SPECIFICATION */
+ C(0xc800, MVCOS, SSF, MVCOS, la1, a2, 0, 0, mvcos, 0)
/* MOVE WITH OFFSET */
/* Really format SS_b, but we pack both lengths into one argument
for the helper call, so we might as well leave one 8-bit field. */
diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c
index 80caab9..6125725 100644
--- a/target/s390x/mem_helper.c
+++ b/target/s390x/mem_helper.c
@@ -110,6 +110,20 @@ static inline void cpu_stsize_data_ra(CPUS390XState *env, uint64_t addr,
}
}
+static inline uint64_t wrap_address(CPUS390XState *env, uint64_t a)
+{
+ if (!(env->psw.mask & PSW_MASK_64)) {
+ if (!(env->psw.mask & PSW_MASK_32)) {
+ /* 24-Bit mode */
+ a &= 0x00ffffff;
+ } else {
+ /* 31-Bit mode */
+ a &= 0x7fffffff;
+ }
+ }
+ return a;
+}
+
static void fast_memset(CPUS390XState *env, uint64_t dest, uint8_t byte,
uint32_t l, uintptr_t ra)
{
@@ -133,6 +147,68 @@ static void fast_memset(CPUS390XState *env, uint64_t dest, uint8_t byte,
}
}
+#ifndef CONFIG_USER_ONLY
+static void fast_memmove_idx(CPUS390XState *env, uint64_t dest, uint64_t src,
+ uint32_t len, int dest_idx, int src_idx,
+ uintptr_t ra)
+{
+ TCGMemOpIdx oi_dest = make_memop_idx(MO_UB, dest_idx);
+ TCGMemOpIdx oi_src = make_memop_idx(MO_UB, src_idx);
+ uint32_t len_adj;
+ void *src_p;
+ void *dest_p;
+ uint8_t x;
+
+ while (len > 0) {
+ src = wrap_address(env, src);
+ dest = wrap_address(env, dest);
+ src_p = tlb_vaddr_to_host(env, src, MMU_DATA_LOAD, src_idx);
+ dest_p = tlb_vaddr_to_host(env, dest, MMU_DATA_STORE, dest_idx);
+
+ if (src_p && dest_p) {
+ /* Access to both whole pages granted. */
+ len_adj = adj_len_to_page(adj_len_to_page(len, src), dest);
+ memmove(dest_p, src_p, len_adj);
+ } else {
+ /* We failed to get access to one or both whole pages. The next
+ read or write access will likely fill the QEMU TLB for the
+ next iteration. */
+ len_adj = 1;
+ x = helper_ret_ldub_mmu(env, src, oi_src, ra);
+ helper_ret_stb_mmu(env, dest, x, oi_dest, ra);
+ }
+ src += len_adj;
+ dest += len_adj;
+ len -= len_adj;
+ }
+}
+
+static int mmu_idx_from_as(uint8_t as)
+{
+ switch (as) {
+ case AS_PRIMARY:
+ return MMU_PRIMARY_IDX;
+ case AS_SECONDARY:
+ return MMU_SECONDARY_IDX;
+ case AS_HOME:
+ return MMU_HOME_IDX;
+ default:
+ /* FIXME AS_ACCREG */
+ g_assert_not_reached();
+ }
+}
+
+static void fast_memmove_as(CPUS390XState *env, uint64_t dest, uint64_t src,
+ uint32_t len, uint8_t dest_as, uint8_t src_as,
+ uintptr_t ra)
+{
+ int src_idx = mmu_idx_from_as(src_as);
+ int dest_idx = mmu_idx_from_as(dest_as);
+
+ fast_memmove_idx(env, dest, src, len, dest_idx, src_idx, ra);
+}
+#endif
+
static void fast_memmove(CPUS390XState *env, uint64_t dest, uint64_t src,
uint32_t l, uintptr_t ra)
{
@@ -408,20 +484,6 @@ uint32_t HELPER(clm)(CPUS390XState *env, uint32_t r1, uint32_t mask,
return cc;
}
-static inline uint64_t wrap_address(CPUS390XState *env, uint64_t a)
-{
- if (!(env->psw.mask & PSW_MASK_64)) {
- if (!(env->psw.mask & PSW_MASK_32)) {
- /* 24-Bit mode */
- a &= 0x00ffffff;
- } else {
- /* 31-Bit mode */
- a &= 0x7fffffff;
- }
- }
- return a;
-}
-
static inline uint64_t get_address(CPUS390XState *env, int reg)
{
return wrap_address(env, env->regs[reg]);
@@ -1789,3 +1851,94 @@ void HELPER(ex)(CPUS390XState *env, uint32_t ilen, uint64_t r1, uint64_t addr)
that requires such execution. */
env->ex_value = insn | ilen;
}
+
+uint32_t HELPER(mvcos)(CPUS390XState *env, uint64_t dest, uint64_t src,
+ uint64_t len)
+{
+ const uint8_t psw_key = (env->psw.mask & PSW_MASK_KEY) >> PSW_SHIFT_KEY;
+ const uint8_t psw_as = (env->psw.mask & PSW_MASK_ASC) >> PSW_SHIFT_ASC;
+ const uint64_t r0 = env->regs[0];
+ const uintptr_t ra = GETPC();
+ CPUState *cs = CPU(s390_env_get_cpu(env));
+ uint8_t dest_key, dest_as, dest_k, dest_a;
+ uint8_t src_key, src_as, src_k, src_a;
+ uint64_t val;
+ int cc = 0;
+
+ HELPER_LOG("%s dest %" PRIx64 ", src %" PRIx64 ", len %" PRIx64 "\n",
+ __func__, dest, src, len);
+
+ if (!(env->psw.mask & PSW_MASK_DAT)) {
+ cpu_restore_state(cs, ra);
+ program_interrupt(env, PGM_SPECIAL_OP, 6);
+ }
+
+ /* OAC (operand access control) for the first operand -> dest */
+ val = (r0 & 0xffff0000ULL) >> 16;
+ dest_key = (val >> 12) & 0xf;
+ dest_as = (val >> 6) & 0x3;
+ dest_k = (val >> 1) & 0x1;
+ dest_a = val & 0x1;
+
+ /* OAC (operand access control) for the second operand -> src */
+ val = (r0 & 0x0000ffffULL);
+ src_key = (val >> 12) & 0xf;
+ src_as = (val >> 6) & 0x3;
+ src_k = (val >> 1) & 0x1;
+ src_a = val & 0x1;
+
+ if (!dest_k) {
+ dest_key = psw_key;
+ }
+ if (!src_k) {
+ src_key = psw_key;
+ }
+ if (!dest_a) {
+ dest_as = psw_as;
+ }
+ if (!src_a) {
+ src_as = psw_as;
+ }
+
+ if (dest_a && dest_as == AS_HOME && (env->psw.mask & PSW_MASK_PSTATE)) {
+ cpu_restore_state(cs, ra);
+ program_interrupt(env, PGM_SPECIAL_OP, 6);
+ }
+ if (!(env->cregs[0] & CR0_SECONDARY) &&
+ (dest_as == AS_SECONDARY || src_as == AS_SECONDARY)) {
+ cpu_restore_state(cs, ra);
+ program_interrupt(env, PGM_SPECIAL_OP, 6);
+ }
+ if (!psw_key_valid(env, dest_key) || !psw_key_valid(env, src_key)) {
+ cpu_restore_state(cs, ra);
+ program_interrupt(env, PGM_PRIVILEGED, 6);
+ }
+
+ len = wrap_length(env, len);
+ if (len > 4096) {
+ cc = 3;
+ len = 4096;
+ }
+
+ /* FIXME: AR-mode and proper problem state mode (using PSW keys) missing */
+ if (src_as == AS_ACCREG || dest_as == AS_ACCREG ||
+ (env->psw.mask & PSW_MASK_PSTATE)) {
+ qemu_log_mask(LOG_UNIMP, "%s: AR-mode and PSTATE support missing\n",
+ __func__);
+ cpu_restore_state(cs, ra);
+ program_interrupt(env, PGM_ADDRESSING, 6);
+ }
+
+ /* FIXME: a) LAP
+ * b) Access using correct keys
+ * c) AR-mode
+ */
+#ifdef CONFIG_USER_ONLY
+ /* psw keys are never valid in user mode, we will never reach this */
+ g_assert_not_reached();
+#else
+ fast_memmove_as(env, dest, src, len, dest_as, src_as, ra);
+#endif
+
+ return cc;
+}
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 204b52a..66254e7 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -3039,6 +3039,14 @@ static ExitStatus op_mvclu(DisasContext *s, DisasOps *o)
return NO_EXIT;
}
+static ExitStatus op_mvcos(DisasContext *s, DisasOps *o)
+{
+ int r3 = get_field(s->fields, r3);
+ gen_helper_mvcos(cc_op, cpu_env, o->addr1, o->in2, regs[r3]);
+ set_cc_static(s);
+ return NO_EXIT;
+}
+
#ifndef CONFIG_USER_ONLY
static ExitStatus op_mvcp(DisasContext *s, DisasOps *o)
{
@@ -5408,6 +5416,7 @@ enum DisasInsnEnum {
#define FAC_SCF S390_FEAT_STORE_CLOCK_FAST
#define FAC_SFLE S390_FEAT_STFLE
#define FAC_ILA S390_FEAT_STFLE_45 /* interlocked-access-facility 1 */
+#define FAC_MVCOS S390_FEAT_MOVE_WITH_OPTIONAL_SPEC
#define FAC_LPP S390_FEAT_SET_PROGRAM_PARAMETERS /* load-program-parameter */
#define FAC_DAT_ENH S390_FEAT_DAT_ENH
#define FAC_E2 S390_FEAT_EXTENDED_TRANSLATION_2
--
2.9.4
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Qemu-devel] [PATCH v3 04/18] target/s390x: Implement CSST
2017-06-20 0:03 [Qemu-devel] [PATCH v3 00/18] target/s390x improvements Richard Henderson
` (2 preceding siblings ...)
2017-06-20 0:03 ` [Qemu-devel] [PATCH v3 03/18] target/s390x: implement mvcos instruction Richard Henderson
@ 2017-06-20 0:03 ` Richard Henderson
2017-06-20 0:03 ` [Qemu-devel] [PATCH v3 05/18] target/s390x: Mark FPSEH facility as available Richard Henderson
` (14 subsequent siblings)
18 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2017-06-20 0:03 UTC (permalink / raw)
To: qemu-devel; +Cc: thuth, aurelien
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target/s390x/cpu_models.c | 2 +
target/s390x/helper.h | 1 +
target/s390x/insn-data.def | 2 +
target/s390x/mem_helper.c | 189 +++++++++++++++++++++++++++++++++++++++++++++
target/s390x/translate.c | 13 +++-
5 files changed, 206 insertions(+), 1 deletion(-)
diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c
index c3a4ce6..68fa481 100644
--- a/target/s390x/cpu_models.c
+++ b/target/s390x/cpu_models.c
@@ -683,6 +683,8 @@ static void add_qemu_cpu_model_features(S390FeatBitmap fbm)
S390_FEAT_ETF2_ENH,
S390_FEAT_STORE_CLOCK_FAST,
S390_FEAT_MOVE_WITH_OPTIONAL_SPEC,
+ S390_FEAT_COMPARE_AND_SWAP_AND_STORE,
+ S390_FEAT_COMPARE_AND_SWAP_AND_STORE_2,
S390_FEAT_GENERAL_INSTRUCTIONS_EXT,
S390_FEAT_EXECUTE_EXT,
S390_FEAT_STFLE_45,
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index b268367..456aaa9 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -33,6 +33,7 @@ DEF_HELPER_3(celgb, i64, env, i64, i32)
DEF_HELPER_3(cdlgb, i64, env, i64, i32)
DEF_HELPER_3(cxlgb, i64, env, i64, i32)
DEF_HELPER_4(cdsg, void, env, i64, i32, i32)
+DEF_HELPER_4(csst, i32, env, i32, i64, i64)
DEF_HELPER_FLAGS_3(aeb, TCG_CALL_NO_WG, i64, env, i64, i64)
DEF_HELPER_FLAGS_3(adb, TCG_CALL_NO_WG, i64, env, i64, i64)
DEF_HELPER_FLAGS_5(axb, TCG_CALL_NO_WG, i64, env, i64, i64, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index aa4c5b2..ef02a8e 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -256,6 +256,8 @@
D(0xbb00, CDS, RS_a, Z, r3_D32, r1_D32, new, r1_D32, cs, 0, MO_TEQ)
D(0xeb31, CDSY, RSY_a, LD, r3_D32, r1_D32, new, r1_D32, cs, 0, MO_TEQ)
C(0xeb3e, CDSG, RSY_a, Z, 0, 0, 0, 0, cdsg, 0)
+/* COMPARE AND SWAP AND STORE */
+ C(0xc802, CSST, SSF, CASS, la1, a2, 0, 0, csst, 0)
/* COMPARE AND TRAP */
D(0xb972, CRT, RRF_c, GIE, r1_32s, r2_32s, 0, 0, ct, 0, 0)
diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c
index 6125725..4a7d770 100644
--- a/target/s390x/mem_helper.c
+++ b/target/s390x/mem_helper.c
@@ -1344,6 +1344,195 @@ void HELPER(cdsg)(CPUS390XState *env, uint64_t addr,
env->regs[r1 + 1] = int128_getlo(oldv);
}
+uint32_t HELPER(csst)(CPUS390XState *env, uint32_t r3, uint64_t a1, uint64_t a2)
+{
+#if !defined(CONFIG_USER_ONLY) || defined(CONFIG_ATOMIC128)
+ uint32_t mem_idx = cpu_mmu_index(env, false);
+#endif
+ uintptr_t ra = GETPC();
+ uint32_t fc = extract32(env->regs[0], 0, 8);
+ uint32_t sc = extract32(env->regs[0], 8, 8);
+ uint64_t pl = get_address(env, 1) & -16;
+ uint64_t svh, svl;
+ uint32_t cc;
+
+ /* Sanity check the function code and storage characteristic. */
+ if (fc > 1 || sc > 3) {
+ if (!s390_has_feat(S390_FEAT_COMPARE_AND_SWAP_AND_STORE_2)) {
+ goto spec_exception;
+ }
+ if (fc > 2 || sc > 4 || (fc == 2 && (r3 & 1))) {
+ goto spec_exception;
+ }
+ }
+
+ /* Sanity check the alignments. */
+ if (extract32(a1, 0, 4 << fc) || extract32(a2, 0, 1 << sc)) {
+ goto spec_exception;
+ }
+
+ /* Sanity check writability of the store address. */
+#ifndef CONFIG_USER_ONLY
+ probe_write(env, a2, mem_idx, ra);
+#endif
+
+ /* Note that the compare-and-swap is atomic, and the store is atomic, but
+ the complete operation is not. Therefore we do not need to assert serial
+ context in order to implement this. That said, restart early if we can't
+ support either operation that is supposed to be atomic. */
+ if (parallel_cpus) {
+ int mask = 0;
+#if !defined(CONFIG_ATOMIC64)
+ mask = -8;
+#elif !defined(CONFIG_ATOMIC128)
+ mask = -16;
+#endif
+ if (((4 << fc) | (1 << sc)) & mask) {
+ cpu_loop_exit_atomic(ENV_GET_CPU(env), ra);
+ }
+ }
+
+ /* All loads happen before all stores. For simplicity, load the entire
+ store value area from the parameter list. */
+ svh = cpu_ldq_data_ra(env, pl + 16, ra);
+ svl = cpu_ldq_data_ra(env, pl + 24, ra);
+
+ switch (fc) {
+ case 0:
+ {
+ uint32_t nv = cpu_ldl_data_ra(env, pl, ra);
+ uint32_t cv = env->regs[r3];
+ uint32_t ov;
+
+ if (parallel_cpus) {
+#ifdef CONFIG_USER_ONLY
+ uint32_t *haddr = g2h(a1);
+ ov = atomic_cmpxchg__nocheck(haddr, cv, nv);
+#else
+ TCGMemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mem_idx);
+ ov = helper_atomic_cmpxchgl_be_mmu(env, a1, cv, nv, oi, ra);
+#endif
+ } else {
+ ov = cpu_ldl_data_ra(env, a1, ra);
+ cpu_stl_data_ra(env, a1, (ov == cv ? nv : ov), ra);
+ }
+ cc = (ov != cv);
+ env->regs[r3] = deposit64(env->regs[r3], 32, 32, ov);
+ }
+ break;
+
+ case 1:
+ {
+ uint64_t nv = cpu_ldq_data_ra(env, pl, ra);
+ uint64_t cv = env->regs[r3];
+ uint64_t ov;
+
+ if (parallel_cpus) {
+#ifdef CONFIG_USER_ONLY
+# ifdef CONFIG_ATOMIC64
+ uint64_t *haddr = g2h(a1);
+ ov = atomic_cmpxchg__nocheck(haddr, cv, nv);
+# else
+ /* Note that we asserted !parallel_cpus above. */
+ g_assert_not_reached();
+# endif
+#else
+ TCGMemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN, mem_idx);
+ ov = helper_atomic_cmpxchgq_be_mmu(env, a1, cv, nv, oi, ra);
+#endif
+ } else {
+ ov = cpu_ldq_data_ra(env, a1, ra);
+ cpu_stq_data_ra(env, a1, (ov == cv ? nv : ov), ra);
+ }
+ cc = (ov != cv);
+ env->regs[r3] = ov;
+ }
+ break;
+
+ case 2:
+ {
+ uint64_t nvh = cpu_ldq_data_ra(env, pl, ra);
+ uint64_t nvl = cpu_ldq_data_ra(env, pl + 8, ra);
+ Int128 nv = int128_make128(nvl, nvh);
+ Int128 cv = int128_make128(env->regs[r3 + 1], env->regs[r3]);
+ Int128 ov;
+
+ if (parallel_cpus) {
+#ifdef CONFIG_ATOMIC128
+ TCGMemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx);
+ ov = helper_atomic_cmpxchgo_be_mmu(env, a1, cv, nv, oi, ra);
+ cc = !int128_eq(ov, cv);
+#else
+ /* Note that we asserted !parallel_cpus above. */
+ g_assert_not_reached();
+#endif
+ } else {
+ uint64_t oh = cpu_ldq_data_ra(env, a1 + 0, ra);
+ uint64_t ol = cpu_ldq_data_ra(env, a1 + 8, ra);
+
+ ov = int128_make128(ol, oh);
+ cc = !int128_eq(ov, cv);
+ if (cc) {
+ nv = ov;
+ }
+
+ cpu_stq_data_ra(env, a1 + 0, int128_gethi(nv), ra);
+ cpu_stq_data_ra(env, a1 + 8, int128_getlo(nv), ra);
+ }
+
+ env->regs[r3 + 0] = int128_gethi(ov);
+ env->regs[r3 + 1] = int128_getlo(ov);
+ }
+ break;
+
+ default:
+ g_assert_not_reached();
+ }
+
+ /* Store only if the comparison succeeded. Note that above we use a pair
+ of 64-bit big-endian loads, so for sc < 3 we must extract the value
+ from the most-significant bits of svh. */
+ if (cc == 0) {
+ switch (sc) {
+ case 0:
+ cpu_stb_data_ra(env, a2, svh >> 56, ra);
+ break;
+ case 1:
+ cpu_stw_data_ra(env, a2, svh >> 48, ra);
+ break;
+ case 2:
+ cpu_stl_data_ra(env, a2, svh >> 32, ra);
+ break;
+ case 3:
+ cpu_stq_data_ra(env, a2, svh, ra);
+ break;
+ case 4:
+ if (parallel_cpus) {
+#ifdef CONFIG_ATOMIC128
+ TCGMemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx);
+ Int128 sv = int128_make128(svl, svh);
+ helper_atomic_sto_be_mmu(env, a2, sv, oi, ra);
+#else
+ /* Note that we asserted !parallel_cpus above. */
+ g_assert_not_reached();
+#endif
+ } else {
+ cpu_stq_data_ra(env, a2 + 0, svh, ra);
+ cpu_stq_data_ra(env, a2 + 8, svl, ra);
+ }
+ default:
+ g_assert_not_reached();
+ }
+ }
+
+ return cc;
+
+ spec_exception:
+ cpu_restore_state(ENV_GET_CPU(env), ra);
+ program_interrupt(env, PGM_SPECIFICATION, 6);
+ g_assert_not_reached();
+}
+
#if !defined(CONFIG_USER_ONLY)
void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
{
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 66254e7..95f2f9d 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -2031,6 +2031,18 @@ static ExitStatus op_cdsg(DisasContext *s, DisasOps *o)
return NO_EXIT;
}
+static ExitStatus op_csst(DisasContext *s, DisasOps *o)
+{
+ int r3 = get_field(s->fields, r3);
+ TCGv_i32 t_r3 = tcg_const_i32(r3);
+
+ gen_helper_csst(cc_op, cpu_env, t_r3, o->in1, o->in2);
+ tcg_temp_free_i32(t_r3);
+
+ set_cc_static(s);
+ return NO_EXIT;
+}
+
#ifndef CONFIG_USER_ONLY
static ExitStatus op_csp(DisasContext *s, DisasOps *o)
{
@@ -5395,7 +5407,6 @@ enum DisasInsnEnum {
/* Give smaller names to the various facilities. */
#define FAC_Z S390_FEAT_ZARCH
#define FAC_CASS S390_FEAT_COMPARE_AND_SWAP_AND_STORE
-#define FAC_CASS2 S390_FEAT_COMPARE_AND_SWAP_AND_STORE_2
#define FAC_DFP S390_FEAT_DFP
#define FAC_DFPR S390_FEAT_FLOATING_POINT_SUPPPORT_ENH /* DFP-rounding */
#define FAC_DO S390_FEAT_STFLE_45 /* distinct-operands */
--
2.9.4
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Qemu-devel] [PATCH v3 05/18] target/s390x: Mark FPSEH facility as available
2017-06-20 0:03 [Qemu-devel] [PATCH v3 00/18] target/s390x improvements Richard Henderson
` (3 preceding siblings ...)
2017-06-20 0:03 ` [Qemu-devel] [PATCH v3 04/18] target/s390x: Implement CSST Richard Henderson
@ 2017-06-20 0:03 ` Richard Henderson
2017-06-23 10:59 ` Aurelien Jarno
2017-06-20 0:03 ` [Qemu-devel] [PATCH v3 06/18] target/s390x: Implement load-on-condition-2 insns Richard Henderson
` (13 subsequent siblings)
18 siblings, 1 reply; 40+ messages in thread
From: Richard Henderson @ 2017-06-20 0:03 UTC (permalink / raw)
To: qemu-devel; +Cc: thuth, aurelien
This facility bit includes DFP-rounding, FPR-GR-transfer,
FPS-sign-handling, and IEEE-exception-simulation. We do
support all of these.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target/s390x/cpu_models.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c
index 68fa481..703feca 100644
--- a/target/s390x/cpu_models.c
+++ b/target/s390x/cpu_models.c
@@ -687,6 +687,7 @@ static void add_qemu_cpu_model_features(S390FeatBitmap fbm)
S390_FEAT_COMPARE_AND_SWAP_AND_STORE_2,
S390_FEAT_GENERAL_INSTRUCTIONS_EXT,
S390_FEAT_EXECUTE_EXT,
+ S390_FEAT_FLOATING_POINT_SUPPPORT_ENH,
S390_FEAT_STFLE_45,
};
int i;
--
2.9.4
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Qemu-devel] [PATCH v3 06/18] target/s390x: Implement load-on-condition-2 insns
2017-06-20 0:03 [Qemu-devel] [PATCH v3 00/18] target/s390x improvements Richard Henderson
` (4 preceding siblings ...)
2017-06-20 0:03 ` [Qemu-devel] [PATCH v3 05/18] target/s390x: Mark FPSEH facility as available Richard Henderson
@ 2017-06-20 0:03 ` Richard Henderson
2017-06-23 11:00 ` Aurelien Jarno
2017-06-20 0:03 ` [Qemu-devel] [PATCH v3 08/18] target/s390x: Mark STFLE_53 facility as available Richard Henderson
` (12 subsequent siblings)
18 siblings, 1 reply; 40+ messages in thread
From: Richard Henderson @ 2017-06-20 0:03 UTC (permalink / raw)
To: qemu-devel; +Cc: thuth, aurelien
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target/s390x/insn-data.def | 9 +++++++++
target/s390x/insn-format.def | 1 +
target/s390x/translate.c | 18 +++++++++++++++---
3 files changed, 25 insertions(+), 3 deletions(-)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index ef02a8e..60d244f 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -516,6 +516,13 @@
C(0xb9e2, LOCGR, RRF_c, LOC, r1, r2, r1, 0, loc, 0)
C(0xebf2, LOC, RSY_b, LOC, r1, m2_32u, new, r1_32, loc, 0)
C(0xebe2, LOCG, RSY_b, LOC, r1, m2_64, r1, 0, loc, 0)
+/* LOAD HALFWORD IMMEDIATE ON CONDITION */
+ C(0xec42, LOCHI, RIE_g, LOC2, r1, i2, new, r1_32, loc, 0)
+ C(0xec46, LOCGHI, RIE_g, LOC2, r1, i2, r1, 0, loc, 0)
+ C(0xec4e, LOCHHI, RIE_g, LOC2, r1_sr32, i2, new, r1_32h, loc, 0)
+/* LOAD HIGH ON CONDITION */
+ C(0xb9e0, LOCFHR, RRF_c, LOC2, r1_sr32, r2, new, r1_32h, loc, 0)
+ C(0xebe0, LOCFH, RSY_b, LOC2, r1_sr32, m2_32u, new, r1_32h, loc, 0)
/* LOAD PAIR DISJOINT */
D(0xc804, LPD, SSF, ILA, 0, 0, new_P, r3_P32, lpd, 0, MO_TEUL)
D(0xc805, LPDG, SSF, ILA, 0, 0, new_P, r3_P64, lpd, 0, MO_TEQ)
@@ -781,6 +788,8 @@
/* STORE ON CONDITION */
D(0xebf3, STOC, RSY_b, LOC, 0, 0, 0, 0, soc, 0, 0)
D(0xebe3, STOCG, RSY_b, LOC, 0, 0, 0, 0, soc, 0, 1)
+/* STORE HIGH ON CONDITION */
+ D(0xebe1, STOCFH, RSY_b, LOC2, 0, 0, 0, 0, soc, 0, 2)
/* STORE REVERSED */
C(0xe33f, STRVH, RXY_a, Z, la2, r1_16u, new, m1_16, rev16, 0)
C(0xe33e, STRV, RXY_a, Z, la2, r1_32u, new, m1_32, rev32, 0)
diff --git a/target/s390x/insn-format.def b/target/s390x/insn-format.def
index 0e898b9..a412d90 100644
--- a/target/s390x/insn-format.def
+++ b/target/s390x/insn-format.def
@@ -11,6 +11,7 @@ F4(RIE_c, R(1, 8), I(2,32, 8), M(3,12), I(4,16,16))
F3(RIE_d, R(1, 8), I(2,16,16), R(3,12))
F3(RIE_e, R(1, 8), I(2,16,16), R(3,12))
F5(RIE_f, R(1, 8), R(2,12), I(3,16,8), I(4,24,8), I(5,32,8))
+F3(RIE_g, R(1, 8), I(2,16,16), M(3,12))
F2(RIL_a, R(1, 8), I(2,16,32))
F2(RIL_b, R(1, 8), I(2,16,32))
F2(RIL_c, M(1, 8), I(2,16,32))
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 95f2f9d..a3234f7 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -3651,7 +3651,7 @@ static ExitStatus op_sigp(DisasContext *s, DisasOps *o)
static ExitStatus op_soc(DisasContext *s, DisasOps *o)
{
DisasCompare c;
- TCGv_i64 a;
+ TCGv_i64 a, h;
TCGLabel *lab;
int r1;
@@ -3671,10 +3671,21 @@ static ExitStatus op_soc(DisasContext *s, DisasOps *o)
r1 = get_field(s->fields, r1);
a = get_address(s, 0, get_field(s->fields, b2), get_field(s->fields, d2));
- if (s->insn->data) {
+ switch (s->insn->data) {
+ case 1: /* STOCG */
tcg_gen_qemu_st64(regs[r1], a, get_mem_index(s));
- } else {
+ break;
+ case 0: /* STOC */
tcg_gen_qemu_st32(regs[r1], a, get_mem_index(s));
+ break;
+ case 2: /* STOCFH */
+ h = tcg_temp_new_i64();
+ tcg_gen_shri_i64(h, regs[r1], 32);
+ tcg_gen_qemu_st32(h, a, get_mem_index(s));
+ tcg_temp_free_i64(h);
+ break;
+ default:
+ g_assert_not_reached();
}
tcg_temp_free_i64(a);
@@ -5422,6 +5433,7 @@ enum DisasInsnEnum {
#define FAC_MIE S390_FEAT_STFLE_49 /* misc-instruction-extensions */
#define FAC_LAT S390_FEAT_STFLE_49 /* load-and-trap */
#define FAC_LOC S390_FEAT_STFLE_45 /* load/store on condition 1 */
+#define FAC_LOC2 S390_FEAT_STFLE_53 /* load/store on condition 2 */
#define FAC_LD S390_FEAT_LONG_DISPLACEMENT
#define FAC_PC S390_FEAT_STFLE_45 /* population count */
#define FAC_SCF S390_FEAT_STORE_CLOCK_FAST
--
2.9.4
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Qemu-devel] [PATCH v3 08/18] target/s390x: Mark STFLE_53 facility as available
2017-06-20 0:03 [Qemu-devel] [PATCH v3 00/18] target/s390x improvements Richard Henderson
` (5 preceding siblings ...)
2017-06-20 0:03 ` [Qemu-devel] [PATCH v3 06/18] target/s390x: Implement load-on-condition-2 insns Richard Henderson
@ 2017-06-20 0:03 ` Richard Henderson
2017-06-23 11:01 ` Aurelien Jarno
2017-06-20 0:03 ` [Qemu-devel] [PATCH v3 10/18] target/s390x: Implement processor-assist insn Richard Henderson
` (11 subsequent siblings)
18 siblings, 1 reply; 40+ messages in thread
From: Richard Henderson @ 2017-06-20 0:03 UTC (permalink / raw)
To: qemu-devel; +Cc: thuth, aurelien
This facility bit includes load-on-condition-2 and
load-and-zero-rightmost-byte.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target/s390x/cpu_models.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c
index 703feca..1db814b 100644
--- a/target/s390x/cpu_models.c
+++ b/target/s390x/cpu_models.c
@@ -689,6 +689,7 @@ static void add_qemu_cpu_model_features(S390FeatBitmap fbm)
S390_FEAT_EXECUTE_EXT,
S390_FEAT_FLOATING_POINT_SUPPPORT_ENH,
S390_FEAT_STFLE_45,
+ S390_FEAT_STFLE_53,
};
int i;
--
2.9.4
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Qemu-devel] [PATCH v3 10/18] target/s390x: Implement processor-assist insn
2017-06-20 0:03 [Qemu-devel] [PATCH v3 00/18] target/s390x improvements Richard Henderson
` (6 preceding siblings ...)
2017-06-20 0:03 ` [Qemu-devel] [PATCH v3 08/18] target/s390x: Mark STFLE_53 facility as available Richard Henderson
@ 2017-06-20 0:03 ` Richard Henderson
2017-06-23 11:01 ` Aurelien Jarno
2017-06-20 0:03 ` [Qemu-devel] [PATCH v3 11/18] target/s390x: Mark STFLE_49 facility as available Richard Henderson
` (10 subsequent siblings)
18 siblings, 1 reply; 40+ messages in thread
From: Richard Henderson @ 2017-06-20 0:03 UTC (permalink / raw)
To: qemu-devel; +Cc: thuth, aurelien
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target/s390x/insn-data.def | 3 +++
target/s390x/translate.c | 1 +
2 files changed, 4 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index b64d465..9c8f184 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -700,6 +700,9 @@
/* Implemented as nops of course. */
C(0xe336, PFD, RXY_b, GIE, 0, 0, 0, 0, 0, 0)
C(0xc602, PFDRL, RIL_c, GIE, 0, 0, 0, 0, 0, 0)
+/* PERFORM PROCESSOR ASSIST */
+ /* Implemented as nop of course. */
+ C(0xb2e8, PPA, RRF_c, PPA, 0, 0, 0, 0, 0, 0)
/* POPULATION COUNT */
C(0xb9e1, POPCNT, RRE, PC, 0, r2_o, r1, 0, popcnt, nz64)
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index b2e58c5..3ffb304 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -5450,6 +5450,7 @@ enum DisasInsnEnum {
#define FAC_DAT_ENH S390_FEAT_DAT_ENH
#define FAC_E2 S390_FEAT_EXTENDED_TRANSLATION_2
#define FAC_EH S390_FEAT_STFLE_49 /* execution-hint */
+#define FAC_PPA S390_FEAT_STFLE_49 /* processor-assist */
#define FAC_LZRB S390_FEAT_STFLE_53 /* load-and-zero-rightmost-byte */
static const DisasInsn insn_info[] = {
--
2.9.4
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Qemu-devel] [PATCH v3 11/18] target/s390x: Mark STFLE_49 facility as available
2017-06-20 0:03 [Qemu-devel] [PATCH v3 00/18] target/s390x improvements Richard Henderson
` (7 preceding siblings ...)
2017-06-20 0:03 ` [Qemu-devel] [PATCH v3 10/18] target/s390x: Implement processor-assist insn Richard Henderson
@ 2017-06-20 0:03 ` Richard Henderson
2017-06-23 11:01 ` Aurelien Jarno
2017-06-20 0:03 ` [Qemu-devel] [PATCH v3 12/18] target/s390x: Finish implementing ETF2-ENH Richard Henderson
` (9 subsequent siblings)
18 siblings, 1 reply; 40+ messages in thread
From: Richard Henderson @ 2017-06-20 0:03 UTC (permalink / raw)
To: qemu-devel; +Cc: thuth, aurelien
This facility bit includes execution-hint, load-and-trap,
miscellaneous-instruction-extensions and processor-assist.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target/s390x/cpu_models.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c
index 1db814b..be7757c 100644
--- a/target/s390x/cpu_models.c
+++ b/target/s390x/cpu_models.c
@@ -689,6 +689,7 @@ static void add_qemu_cpu_model_features(S390FeatBitmap fbm)
S390_FEAT_EXECUTE_EXT,
S390_FEAT_FLOATING_POINT_SUPPPORT_ENH,
S390_FEAT_STFLE_45,
+ S390_FEAT_STFLE_49,
S390_FEAT_STFLE_53,
};
int i;
--
2.9.4
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Qemu-devel] [PATCH v3 12/18] target/s390x: Finish implementing ETF2-ENH
2017-06-20 0:03 [Qemu-devel] [PATCH v3 00/18] target/s390x improvements Richard Henderson
` (8 preceding siblings ...)
2017-06-20 0:03 ` [Qemu-devel] [PATCH v3 11/18] target/s390x: Mark STFLE_49 facility as available Richard Henderson
@ 2017-06-20 0:03 ` Richard Henderson
2017-06-23 11:02 ` Aurelien Jarno
2017-06-20 0:04 ` [Qemu-devel] [PATCH v3 13/18] target/s390x: Implement CONVERT UNICODE insns Richard Henderson
` (8 subsequent siblings)
18 siblings, 1 reply; 40+ messages in thread
From: Richard Henderson @ 2017-06-20 0:03 UTC (permalink / raw)
To: qemu-devel; +Cc: thuth, aurelien
Missed the proper alignment in TRTO/TRTT, and ignoring the M3
field for all TRXX insns without ETF2-ENH.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target/s390x/mem_helper.c | 11 ++++++++++-
target/s390x/translate.c | 5 +++--
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c
index 4a7d770..4376c72 100644
--- a/target/s390x/mem_helper.c
+++ b/target/s390x/mem_helper.c
@@ -1265,13 +1265,22 @@ uint32_t HELPER(trXX)(CPUS390XState *env, uint32_t r1, uint32_t r2,
uintptr_t ra = GETPC();
int dsize = (sizes & 1) ? 1 : 2;
int ssize = (sizes & 2) ? 1 : 2;
- uint64_t tbl = get_address(env, 1) & ~7;
+ uint64_t tbl = get_address(env, 1);
uint64_t dst = get_address(env, r1);
uint64_t len = get_length(env, r1 + 1);
uint64_t src = get_address(env, r2);
uint32_t cc = 3;
int i;
+ /* The lower address bits of TBL are ignored. For TROO, TROT, it's
+ the low 3 bits (double-word aligned). For TRTO, TRTT, it's either
+ the low 12 bits (4K, without ETF2-ENH) or 3 bits (with ETF2-ENH). */
+ if (ssize == 2 && !s390_has_feat(S390_FEAT_ETF2_ENH)) {
+ tbl &= -4096;
+ } else {
+ tbl &= -8;
+ }
+
check_alignment(env, len, ssize, ra);
/* Lest we fail to service interrupts in a timely manner, */
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 3ffb304..630eacb 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -4363,8 +4363,9 @@ static ExitStatus op_trXX(DisasContext *s, DisasOps *o)
TCGv_i32 tst = tcg_temp_new_i32();
int m3 = get_field(s->fields, m3);
- /* XXX: the C bit in M3 should be considered as 0 when the
- ETF2-enhancement facility is not installed. */
+ if (!s390_has_feat(S390_FEAT_ETF2_ENH)) {
+ m3 = 0;
+ }
if (m3 & 1) {
tcg_gen_movi_i32(tst, -1);
} else {
--
2.9.4
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Qemu-devel] [PATCH v3 13/18] target/s390x: Implement CONVERT UNICODE insns
2017-06-20 0:03 [Qemu-devel] [PATCH v3 00/18] target/s390x improvements Richard Henderson
` (9 preceding siblings ...)
2017-06-20 0:03 ` [Qemu-devel] [PATCH v3 12/18] target/s390x: Finish implementing ETF2-ENH Richard Henderson
@ 2017-06-20 0:04 ` Richard Henderson
2017-06-23 15:52 ` Aurelien Jarno
2017-06-20 0:04 ` [Qemu-devel] [PATCH v3 14/18] target/s390x: Tidy SRST Richard Henderson
` (7 subsequent siblings)
18 siblings, 1 reply; 40+ messages in thread
From: Richard Henderson @ 2017-06-20 0:04 UTC (permalink / raw)
To: qemu-devel; +Cc: thuth, aurelien
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target/s390x/helper.h | 6 +
target/s390x/insn-data.def | 13 ++
target/s390x/mem_helper.c | 309 +++++++++++++++++++++++++++++++++++++++++++++
target/s390x/translate.c | 44 +++++++
4 files changed, 372 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 456aaa9..c014820 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -107,6 +107,12 @@ DEF_HELPER_2(stfle, i32, env, i64)
DEF_HELPER_FLAGS_2(lpq, TCG_CALL_NO_WG, i64, env, i64)
DEF_HELPER_FLAGS_4(stpq, TCG_CALL_NO_WG, void, env, i64, i64, i64)
DEF_HELPER_4(mvcos, i32, env, i64, i64, i64)
+DEF_HELPER_4(cu12, i32, env, i32, i32, i32)
+DEF_HELPER_4(cu14, i32, env, i32, i32, i32)
+DEF_HELPER_4(cu21, i32, env, i32, i32, i32)
+DEF_HELPER_4(cu24, i32, env, i32, i32, i32)
+DEF_HELPER_4(cu41, i32, env, i32, i32, i32)
+DEF_HELPER_4(cu42, i32, env, i32, i32, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 9c8f184..634ef98 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -313,6 +313,19 @@
C(0xb3a1, CDLGBR, RRF_e, FPE, 0, r2_o, f1, 0, cdlgb, 0)
C(0xb3a2, CXLGBR, RRF_e, FPE, 0, r2_o, x1, 0, cxlgb, 0)
+/* CONVERT UTF-8 TO UTF-16 */
+ D(0xb2a7, CU12, RRF_c, Z, 0, 0, 0, 0, cuXX, 0, 12)
+/* CONVERT UTF-8 TO UTF-32 */
+ D(0xb9b0, CU14, RRF_c, ETF3, 0, 0, 0, 0, cuXX, 0, 14)
+/* CONVERT UTF-16 to UTF-8 */
+ D(0xb2a6, CU21, RRF_c, Z, 0, 0, 0, 0, cuXX, 0, 21)
+/* CONVERT UTF-16 to UTF-32 */
+ D(0xb9b1, CU24, RRF_c, ETF3, 0, 0, 0, 0, cuXX, 0, 24)
+/* CONVERT UTF-32 to UTF-8 */
+ D(0xb9b3, CU41, RRF_c, ETF3, 0, 0, 0, 0, cuXX, 0, 41)
+/* CONVERT UTF-32 to UTF-16 */
+ D(0xb9b2, CU42, RRF_c, ETF3, 0, 0, 0, 0, cuXX, 0, 42)
+
/* DIVIDE */
C(0x1d00, DR, RR_a, Z, r1_D32, r2_32s, new_P, r1_P32, divs32, 0)
C(0x5d00, D, RX_a, Z, r1_D32, m2_32s, new_P, r1_P32, divs32, 0)
diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c
index 4376c72..df082f5 100644
--- a/target/s390x/mem_helper.c
+++ b/target/s390x/mem_helper.c
@@ -2140,3 +2140,312 @@ uint32_t HELPER(mvcos)(CPUS390XState *env, uint64_t dest, uint64_t src,
return cc;
}
+
+/* Decode a Unicode character. A return value < 0 indicates success, storing
+ the UTF-32 result into OCHAR and the input length into OLEN. A return
+ value >= 0 indicates failure, and the CC value to be returned. */
+typedef int (*decode_unicode_fn)(CPUS390XState *env, uint64_t addr,
+ uint64_t ilen, bool enh_check, uintptr_t ra,
+ uint32_t *ochar, uint32_t *olen);
+
+/* Encode a Unicode character. A return value < 0 indicates success, storing
+ the bytes into ADDR and the output length into OLEN. A return value >= 0
+ indicates failure, and the CC value to be returned. */
+typedef int (*encode_unicode_fn)(CPUS390XState *env, uint64_t addr,
+ uint64_t ilen, uintptr_t ra, uint32_t c,
+ uint32_t *olen);
+
+static int decode_utf8(CPUS390XState *env, uint64_t addr, uint64_t ilen,
+ bool enh_check, uintptr_t ra,
+ uint32_t *ochar, uint32_t *olen)
+{
+ uint8_t s0, s1, s2, s3;
+ uint32_t c, l;
+
+ if (ilen < 1) {
+ return 0;
+ }
+ s0 = cpu_ldub_data_ra(env, addr, ra);
+ if (s0 <= 0x7f) {
+ /* one byte character */
+ l = 1;
+ c = s0;
+ } else if (s0 <= (enh_check ? 0xc1 : 0xbf)) {
+ /* invalid character */
+ return 2;
+ } else if (s0 <= 0xdf) {
+ /* two byte character */
+ l = 2;
+ if (ilen < 2) {
+ return 0;
+ }
+ s1 = cpu_ldub_data_ra(env, addr + 1, ra);
+ c = s0 & 0x1f;
+ c = (c << 6) | (s1 & 0x3f);
+ if (enh_check && (s1 & 0xc0) != 0x80) {
+ return 2;
+ }
+ } else if (s0 <= 0xef) {
+ /* three byte character */
+ l = 3;
+ if (ilen < 3) {
+ return 0;
+ }
+ s1 = cpu_ldub_data_ra(env, addr + 1, ra);
+ s2 = cpu_ldub_data_ra(env, addr + 2, ra);
+ c = s0 & 0x0f;
+ c = (c << 6) | (s1 & 0x3f);
+ c = (c << 6) | (s2 & 0x3f);
+ /* Fold the byte-by-byte range descriptions in the PoO into
+ tests against the complete value. It disallows encodings
+ that could be smaller, and the UTF-16 surrogates. */
+ if (enh_check
+ && ((s1 & 0xc0) != 0x80
+ || (s2 & 0xc0) != 0x80
+ || c < 0x1000
+ || (c >= 0xd800 && c <= 0xdfff))) {
+ return 2;
+ }
+ } else if (s0 <= (enh_check ? 0xf4 : 0xf7)) {
+ /* four byte character */
+ l = 4;
+ if (ilen < 4) {
+ return 0;
+ }
+ s1 = cpu_ldub_data_ra(env, addr + 1, ra);
+ s2 = cpu_ldub_data_ra(env, addr + 2, ra);
+ s3 = cpu_ldub_data_ra(env, addr + 3, ra);
+ c = s0 & 0x0f;
+ c = (c << 6) | (s1 & 0x3f);
+ c = (c << 6) | (s2 & 0x3f);
+ c = (c << 6) | (s3 & 0x3f);
+ /* See above. */
+ if (enh_check
+ && ((s1 & 0xc0) != 0x80
+ || (s2 & 0xc0) != 0x80
+ || c < 0x010000
+ || c > 0x10ffff)) {
+ return 2;
+ }
+ } else {
+ /* invalid character */
+ return 2;
+ }
+
+ *ochar = c;
+ *olen = l;
+ return -1;
+}
+
+static int decode_utf16(CPUS390XState *env, uint64_t addr, uint64_t ilen,
+ bool enh_check, uintptr_t ra,
+ uint32_t *ochar, uint32_t *olen)
+{
+ uint16_t s0, s1;
+ uint32_t c, l;
+
+ if (ilen < 2) {
+ return 0;
+ }
+ s0 = cpu_lduw_data_ra(env, addr, ra);
+ if ((s0 & 0xfc00) != 0xd800) {
+ /* one word character */
+ l = 2;
+ c = s0;
+ } else {
+ /* two word character */
+ l = 4;
+ if (ilen < 4) {
+ return 0;
+ }
+ s1 = cpu_lduw_data_ra(env, addr + 2, ra);
+ c = extract32(s0, 6, 4) + 1;
+ c = (c << 6) | (s0 & 0x3f);
+ c = (c << 10) | (s1 & 0x3ff);
+ if (enh_check && (s1 & 0xfc00) != 0xdc00) {
+ /* invalid surrogate character */
+ return 2;
+ }
+ }
+
+ *ochar = c;
+ *olen = l;
+ return -1;
+}
+
+static int decode_utf32(CPUS390XState *env, uint64_t addr, uint64_t ilen,
+ bool enh_check, uintptr_t ra,
+ uint32_t *ochar, uint32_t *olen)
+{
+ uint32_t c;
+
+ if (ilen < 4) {
+ return 0;
+ }
+ c = cpu_ldl_data_ra(env, addr, ra);
+ if ((c >= 0xd800 && c <= 0xdbff) || c > 0x10ffff) {
+ /* invalid unicode character */
+ return 2;
+ }
+
+ *ochar = c;
+ *olen = 4;
+ return -1;
+}
+
+static int encode_utf8(CPUS390XState *env, uint64_t addr, uint64_t ilen,
+ uintptr_t ra, uint32_t c, uint32_t *olen)
+{
+ uint8_t d[4];
+ uint32_t l, i;
+
+ if (c <= 0x7f) {
+ /* one byte character */
+ l = 1;
+ d[0] = c;
+ } else if (c <= 0x7ff) {
+ /* two byte character */
+ l = 2;
+ d[1] = 0x80 | extract32(c, 0, 6);
+ d[0] = 0xc0 | extract32(c, 6, 5);
+ } else if (c <= 0xffff) {
+ /* three byte character */
+ l = 3;
+ d[2] = 0x80 | extract32(c, 0, 6);
+ d[1] = 0x80 | extract32(c, 6, 6);
+ d[0] = 0xe0 | extract32(c, 12, 4);
+ } else {
+ /* four byte character */
+ l = 4;
+ d[3] = 0x80 | extract32(c, 0, 6);
+ d[2] = 0x80 | extract32(c, 6, 6);
+ d[1] = 0x80 | extract32(c, 12, 6);
+ d[0] = 0xe0 | extract32(c, 18, 3);
+ }
+
+ if (ilen < l) {
+ return 1;
+ }
+ for (i = 0; i < l; ++i) {
+ cpu_stb_data_ra(env, addr + i, d[i], ra);
+ }
+
+ *olen = l;
+ return -1;
+}
+
+static int encode_utf16(CPUS390XState *env, uint64_t addr, uint64_t ilen,
+ uintptr_t ra, uint32_t c, uint32_t *olen)
+{
+ uint16_t d0, d1;
+
+ if (c <= 0xffff) {
+ /* one word character */
+ if (ilen < 2) {
+ return 1;
+ }
+ cpu_stw_data_ra(env, addr, c, ra);
+ *olen = 2;
+ } else {
+ /* two word character */
+ if (ilen < 4) {
+ return 1;
+ }
+ d1 = 0xbc00 | extract32(c, 0, 10);
+ d0 = 0xb800 | extract32(c, 10, 6);
+ d0 = deposit32(d0, 6, 4, extract32(c, 16, 5) - 1);
+ cpu_stw_data_ra(env, addr + 0, d0, ra);
+ cpu_stw_data_ra(env, addr + 2, d1, ra);
+ *olen = 4;
+ }
+
+ return -1;
+}
+
+static int encode_utf32(CPUS390XState *env, uint64_t addr, uint64_t ilen,
+ uintptr_t ra, uint32_t c, uint32_t *olen)
+{
+ if (ilen < 4) {
+ return 1;
+ }
+ cpu_stl_data_ra(env, addr, c, ra);
+ *olen = 4;
+ return -1;
+}
+
+static inline uint32_t convert_unicode(CPUS390XState *env, uint32_t r1,
+ uint32_t r2, uint32_t m3, uintptr_t ra,
+ decode_unicode_fn decode,
+ encode_unicode_fn encode)
+{
+ uint64_t dst = get_address(env, r1);
+ uint64_t dlen = get_length(env, r1 + 1);
+ uint64_t src = get_address(env, r2);
+ uint64_t slen = get_length(env, r2 + 1);
+ bool enh_check = m3 & 1;
+ int cc, i;
+
+ /* Lest we fail to service interrupts in a timely manner, limit the
+ amount of work we're willing to do. For now, let's cap at 256. */
+ for (i = 0; i < 256; ++i) {
+ uint32_t c, ilen, olen;
+
+ cc = decode(env, src, slen, enh_check, ra, &c, &ilen);
+ if (unlikely(cc >= 0)) {
+ break;
+ }
+ cc = encode(env, dst, dlen, ra, c, &olen);
+ if (unlikely(cc >= 0)) {
+ break;
+ }
+
+ src += ilen;
+ slen -= ilen;
+ dst += olen;
+ dlen -= olen;
+ cc = 3;
+ }
+
+ set_address(env, r1, dst);
+ set_length(env, r1 + 1, dlen);
+ set_address(env, r2, src);
+ set_length(env, r2 + 1, slen);
+
+ return cc;
+}
+
+uint32_t HELPER(cu12)(CPUS390XState *env, uint32_t r1, uint32_t r2, uint32_t m3)
+{
+ return convert_unicode(env, r1, r2, m3, GETPC(),
+ decode_utf8, encode_utf16);
+}
+
+uint32_t HELPER(cu14)(CPUS390XState *env, uint32_t r1, uint32_t r2, uint32_t m3)
+{
+ return convert_unicode(env, r1, r2, m3, GETPC(),
+ decode_utf8, encode_utf32);
+}
+
+uint32_t HELPER(cu21)(CPUS390XState *env, uint32_t r1, uint32_t r2, uint32_t m3)
+{
+ return convert_unicode(env, r1, r2, m3, GETPC(),
+ decode_utf16, encode_utf8);
+}
+
+uint32_t HELPER(cu24)(CPUS390XState *env, uint32_t r1, uint32_t r2, uint32_t m3)
+{
+ return convert_unicode(env, r1, r2, m3, GETPC(),
+ decode_utf16, encode_utf32);
+}
+
+uint32_t HELPER(cu41)(CPUS390XState *env, uint32_t r1, uint32_t r2, uint32_t m3)
+{
+ return convert_unicode(env, r1, r2, m3, GETPC(),
+ decode_utf32, encode_utf8);
+}
+
+uint32_t HELPER(cu42)(CPUS390XState *env, uint32_t r1, uint32_t r2, uint32_t m3)
+{
+ return convert_unicode(env, r1, r2, m3, GETPC(),
+ decode_utf32, encode_utf16);
+}
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 630eacb..f8989ec 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -2120,6 +2120,49 @@ static ExitStatus op_ct(DisasContext *s, DisasOps *o)
return NO_EXIT;
}
+static ExitStatus op_cuXX(DisasContext *s, DisasOps *o)
+{
+ int m3 = get_field(s->fields, m3);
+ TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
+ TCGv_i32 r2 = tcg_const_i32(get_field(s->fields, r2));
+ TCGv_i32 chk;
+
+ if (!s390_has_feat(s->insn->fac == S390_FEAT_EXTENDED_TRANSLATION_3
+ ? S390_FEAT_ETF3_ENH : S390_FEAT_ETF2_ENH)) {
+ m3 = 0;
+ }
+ chk = tcg_const_i32(m3);
+
+ switch (s->insn->data) {
+ case 12:
+ gen_helper_cu12(cc_op, cpu_env, r1, r2, chk);
+ break;
+ case 14:
+ gen_helper_cu14(cc_op, cpu_env, r1, r2, chk);
+ break;
+ case 21:
+ gen_helper_cu21(cc_op, cpu_env, r1, r2, chk);
+ break;
+ case 24:
+ gen_helper_cu24(cc_op, cpu_env, r1, r2, chk);
+ break;
+ case 41:
+ gen_helper_cu41(cc_op, cpu_env, r1, r2, chk);
+ break;
+ case 42:
+ gen_helper_cu42(cc_op, cpu_env, r1, r2, chk);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ tcg_temp_free_i32(r1);
+ tcg_temp_free_i32(r2);
+ tcg_temp_free_i32(chk);
+ set_cc_static(s);
+ return NO_EXIT;
+}
+
#ifndef CONFIG_USER_ONLY
static ExitStatus op_diag(DisasContext *s, DisasOps *o)
{
@@ -5453,6 +5496,7 @@ enum DisasInsnEnum {
#define FAC_EH S390_FEAT_STFLE_49 /* execution-hint */
#define FAC_PPA S390_FEAT_STFLE_49 /* processor-assist */
#define FAC_LZRB S390_FEAT_STFLE_53 /* load-and-zero-rightmost-byte */
+#define FAC_ETF3 S390_FEAT_EXTENDED_TRANSLATION_3
static const DisasInsn insn_info[] = {
#include "insn-data.def"
--
2.9.4
^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [Qemu-devel] [PATCH v3 13/18] target/s390x: Implement CONVERT UNICODE insns
2017-06-20 0:04 ` [Qemu-devel] [PATCH v3 13/18] target/s390x: Implement CONVERT UNICODE insns Richard Henderson
@ 2017-06-23 15:52 ` Aurelien Jarno
0 siblings, 0 replies; 40+ messages in thread
From: Aurelien Jarno @ 2017-06-23 15:52 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, thuth
On 2017-06-19 17:04, Richard Henderson wrote:
> diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
> index 9c8f184..634ef98 100644
> --- a/target/s390x/insn-data.def
> +++ b/target/s390x/insn-data.def
> @@ -313,6 +313,19 @@
> C(0xb3a1, CDLGBR, RRF_e, FPE, 0, r2_o, f1, 0, cdlgb, 0)
> C(0xb3a2, CXLGBR, RRF_e, FPE, 0, r2_o, x1, 0, cxlgb, 0)
>
> +/* CONVERT UTF-8 TO UTF-16 */
> + D(0xb2a7, CU12, RRF_c, Z, 0, 0, 0, 0, cuXX, 0, 12)
> +/* CONVERT UTF-8 TO UTF-32 */
> + D(0xb9b0, CU14, RRF_c, ETF3, 0, 0, 0, 0, cuXX, 0, 14)
> +/* CONVERT UTF-16 to UTF-8 */
> + D(0xb2a6, CU21, RRF_c, Z, 0, 0, 0, 0, cuXX, 0, 21)
> +/* CONVERT UTF-16 to UTF-32 */
> + D(0xb9b1, CU24, RRF_c, ETF3, 0, 0, 0, 0, cuXX, 0, 24)
> +/* CONVERT UTF-32 to UTF-8 */
> + D(0xb9b3, CU41, RRF_c, ETF3, 0, 0, 0, 0, cuXX, 0, 41)
> +/* CONVERT UTF-32 to UTF-16 */
> + D(0xb9b2, CU42, RRF_c, ETF3, 0, 0, 0, 0, cuXX, 0, 42)
> +
CU41 and CU42 are inverted here. CU41 has the 0xb9b2 opcode and CU42 the
0xb9b3 opcode.
> diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c
> index 4376c72..df082f5 100644
> --- a/target/s390x/mem_helper.c
> +++ b/target/s390x/mem_helper.c
...
> +static int encode_utf8(CPUS390XState *env, uint64_t addr, uint64_t ilen,
> + uintptr_t ra, uint32_t c, uint32_t *olen)
> +{
> + uint8_t d[4];
> + uint32_t l, i;
> +
> + if (c <= 0x7f) {
> + /* one byte character */
> + l = 1;
> + d[0] = c;
> + } else if (c <= 0x7ff) {
> + /* two byte character */
> + l = 2;
> + d[1] = 0x80 | extract32(c, 0, 6);
> + d[0] = 0xc0 | extract32(c, 6, 5);
> + } else if (c <= 0xffff) {
> + /* three byte character */
> + l = 3;
> + d[2] = 0x80 | extract32(c, 0, 6);
> + d[1] = 0x80 | extract32(c, 6, 6);
> + d[0] = 0xe0 | extract32(c, 12, 4);
> + } else {
> + /* four byte character */
> + l = 4;
> + d[3] = 0x80 | extract32(c, 0, 6);
> + d[2] = 0x80 | extract32(c, 6, 6);
> + d[1] = 0x80 | extract32(c, 12, 6);
> + d[0] = 0xe0 | extract32(c, 18, 3);
This should be 0xf0 instead of 0xe0.
> +static int encode_utf16(CPUS390XState *env, uint64_t addr, uint64_t ilen,
> + uintptr_t ra, uint32_t c, uint32_t *olen)
> +{
> + uint16_t d0, d1;
> +
> + if (c <= 0xffff) {
> + /* one word character */
> + if (ilen < 2) {
> + return 1;
> + }
> + cpu_stw_data_ra(env, addr, c, ra);
> + *olen = 2;
> + } else {
> + /* two word character */
> + if (ilen < 4) {
> + return 1;
> + }
> + d1 = 0xbc00 | extract32(c, 0, 10);
> + d0 = 0xb800 | extract32(c, 10, 6);
This should be 0xdc00 and 0xd800;
Otherwise the patch looks fine to me.
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 40+ messages in thread
* [Qemu-devel] [PATCH v3 14/18] target/s390x: Tidy SRST
2017-06-20 0:03 [Qemu-devel] [PATCH v3 00/18] target/s390x improvements Richard Henderson
` (10 preceding siblings ...)
2017-06-20 0:04 ` [Qemu-devel] [PATCH v3 13/18] target/s390x: Implement CONVERT UNICODE insns Richard Henderson
@ 2017-06-20 0:04 ` Richard Henderson
2017-06-20 7:33 ` David Hildenbrand
2017-06-23 15:52 ` Aurelien Jarno
2017-06-20 0:04 ` [Qemu-devel] [PATCH v3 15/18] target/s390x: Implement SRSTU Richard Henderson
` (6 subsequent siblings)
18 siblings, 2 replies; 40+ messages in thread
From: Richard Henderson @ 2017-06-20 0:04 UTC (permalink / raw)
To: qemu-devel; +Cc: thuth, aurelien
Since we require all registers saved on input, read R0 from ENV instead
of passing it manually. Recognize the specification exception when R0
contains incorrect data.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target/s390x/helper.h | 2 +-
target/s390x/mem_helper.c | 11 ++++++++---
target/s390x/translate.c | 2 +-
3 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index c014820..cd51b89 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -12,7 +12,7 @@ DEF_HELPER_FLAGS_3(divs32, TCG_CALL_NO_WG, s64, env, s64, s64)
DEF_HELPER_FLAGS_3(divu32, TCG_CALL_NO_WG, i64, env, i64, i64)
DEF_HELPER_FLAGS_3(divs64, TCG_CALL_NO_WG, s64, env, s64, s64)
DEF_HELPER_FLAGS_4(divu64, TCG_CALL_NO_WG, i64, env, i64, i64, i64)
-DEF_HELPER_4(srst, i64, env, i64, i64, i64)
+DEF_HELPER_3(srst, i64, env, i64, i64)
DEF_HELPER_4(clst, i64, env, i64, i64, i64)
DEF_HELPER_FLAGS_4(mvn, TCG_CALL_NO_WG, void, env, i32, i64, i64)
DEF_HELPER_FLAGS_4(mvo, TCG_CALL_NO_WG, void, env, i32, i64, i64)
diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c
index df082f5..990858e 100644
--- a/target/s390x/mem_helper.c
+++ b/target/s390x/mem_helper.c
@@ -538,12 +538,17 @@ static inline void set_length(CPUS390XState *env, int reg, uint64_t length)
}
/* search string (c is byte to search, r2 is string, r1 end of string) */
-uint64_t HELPER(srst)(CPUS390XState *env, uint64_t r0, uint64_t end,
- uint64_t str)
+uint64_t HELPER(srst)(CPUS390XState *env, uint64_t end, uint64_t str)
{
uintptr_t ra = GETPC();
uint32_t len;
- uint8_t v, c = r0;
+ uint8_t v, c = env->regs[0];
+
+ /* Bits 32-55 must contain all 0. */
+ if (env->regs[0] & 0xffffff00u) {
+ cpu_restore_state(ENV_GET_CPU(env), ra);
+ program_interrupt(env, PGM_SPECIFICATION, 6);
+ }
str = wrap_address(env, str);
end = wrap_address(env, end);
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index f8989ec..4a860f1 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -4256,7 +4256,7 @@ static ExitStatus op_stpq(DisasContext *s, DisasOps *o)
static ExitStatus op_srst(DisasContext *s, DisasOps *o)
{
- gen_helper_srst(o->in1, cpu_env, regs[0], o->in1, o->in2);
+ gen_helper_srst(o->in1, cpu_env, o->in1, o->in2);
set_cc_static(s);
return_low128(o->in2);
return NO_EXIT;
--
2.9.4
^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [Qemu-devel] [PATCH v3 14/18] target/s390x: Tidy SRST
2017-06-20 0:04 ` [Qemu-devel] [PATCH v3 14/18] target/s390x: Tidy SRST Richard Henderson
@ 2017-06-20 7:33 ` David Hildenbrand
2017-06-23 15:52 ` Aurelien Jarno
1 sibling, 0 replies; 40+ messages in thread
From: David Hildenbrand @ 2017-06-20 7:33 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: thuth, aurelien
On 20.06.2017 02:04, Richard Henderson wrote:
> Since we require all registers saved on input, read R0 from ENV instead
> of passing it manually. Recognize the specification exception when R0
> contains incorrect data.
>
> Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: David Hildenbrand <david@redhat.com>
> ---
> target/s390x/helper.h | 2 +-
> target/s390x/mem_helper.c | 11 ++++++++---
> target/s390x/translate.c | 2 +-
> 3 files changed, 10 insertions(+), 5 deletions(-)
>
> diff --git a/target/s390x/helper.h b/target/s390x/helper.h
> index c014820..cd51b89 100644
> --- a/target/s390x/helper.h
> +++ b/target/s390x/helper.h
> @@ -12,7 +12,7 @@ DEF_HELPER_FLAGS_3(divs32, TCG_CALL_NO_WG, s64, env, s64, s64)
> DEF_HELPER_FLAGS_3(divu32, TCG_CALL_NO_WG, i64, env, i64, i64)
> DEF_HELPER_FLAGS_3(divs64, TCG_CALL_NO_WG, s64, env, s64, s64)
> DEF_HELPER_FLAGS_4(divu64, TCG_CALL_NO_WG, i64, env, i64, i64, i64)
> -DEF_HELPER_4(srst, i64, env, i64, i64, i64)
> +DEF_HELPER_3(srst, i64, env, i64, i64)
> DEF_HELPER_4(clst, i64, env, i64, i64, i64)
> DEF_HELPER_FLAGS_4(mvn, TCG_CALL_NO_WG, void, env, i32, i64, i64)
> DEF_HELPER_FLAGS_4(mvo, TCG_CALL_NO_WG, void, env, i32, i64, i64)
> diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c
> index df082f5..990858e 100644
> --- a/target/s390x/mem_helper.c
> +++ b/target/s390x/mem_helper.c
> @@ -538,12 +538,17 @@ static inline void set_length(CPUS390XState *env, int reg, uint64_t length)
> }
>
> /* search string (c is byte to search, r2 is string, r1 end of string) */
> -uint64_t HELPER(srst)(CPUS390XState *env, uint64_t r0, uint64_t end,
> - uint64_t str)
> +uint64_t HELPER(srst)(CPUS390XState *env, uint64_t end, uint64_t str)
> {
> uintptr_t ra = GETPC();
> uint32_t len;
> - uint8_t v, c = r0;
> + uint8_t v, c = env->regs[0];
> +
> + /* Bits 32-55 must contain all 0. */
> + if (env->regs[0] & 0xffffff00u) {
> + cpu_restore_state(ENV_GET_CPU(env), ra);
> + program_interrupt(env, PGM_SPECIFICATION, 6);
> + }
>
> str = wrap_address(env, str);
> end = wrap_address(env, end);
> diff --git a/target/s390x/translate.c b/target/s390x/translate.c
> index f8989ec..4a860f1 100644
> --- a/target/s390x/translate.c
> +++ b/target/s390x/translate.c
> @@ -4256,7 +4256,7 @@ static ExitStatus op_stpq(DisasContext *s, DisasOps *o)
>
> static ExitStatus op_srst(DisasContext *s, DisasOps *o)
> {
> - gen_helper_srst(o->in1, cpu_env, regs[0], o->in1, o->in2);
> + gen_helper_srst(o->in1, cpu_env, o->in1, o->in2);
> set_cc_static(s);
> return_low128(o->in2);
> return NO_EXIT;
>
--
Thanks,
David
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [Qemu-devel] [PATCH v3 14/18] target/s390x: Tidy SRST
2017-06-20 0:04 ` [Qemu-devel] [PATCH v3 14/18] target/s390x: Tidy SRST Richard Henderson
2017-06-20 7:33 ` David Hildenbrand
@ 2017-06-23 15:52 ` Aurelien Jarno
1 sibling, 0 replies; 40+ messages in thread
From: Aurelien Jarno @ 2017-06-23 15:52 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, thuth
On 2017-06-19 17:04, Richard Henderson wrote:
> Since we require all registers saved on input, read R0 from ENV instead
> of passing it manually. Recognize the specification exception when R0
> contains incorrect data.
>
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target/s390x/helper.h | 2 +-
> target/s390x/mem_helper.c | 11 ++++++++---
> target/s390x/translate.c | 2 +-
> 3 files changed, 10 insertions(+), 5 deletions(-)
>
> diff --git a/target/s390x/helper.h b/target/s390x/helper.h
> index c014820..cd51b89 100644
> --- a/target/s390x/helper.h
> +++ b/target/s390x/helper.h
> @@ -12,7 +12,7 @@ DEF_HELPER_FLAGS_3(divs32, TCG_CALL_NO_WG, s64, env, s64, s64)
> DEF_HELPER_FLAGS_3(divu32, TCG_CALL_NO_WG, i64, env, i64, i64)
> DEF_HELPER_FLAGS_3(divs64, TCG_CALL_NO_WG, s64, env, s64, s64)
> DEF_HELPER_FLAGS_4(divu64, TCG_CALL_NO_WG, i64, env, i64, i64, i64)
> -DEF_HELPER_4(srst, i64, env, i64, i64, i64)
> +DEF_HELPER_3(srst, i64, env, i64, i64)
> DEF_HELPER_4(clst, i64, env, i64, i64, i64)
> DEF_HELPER_FLAGS_4(mvn, TCG_CALL_NO_WG, void, env, i32, i64, i64)
> DEF_HELPER_FLAGS_4(mvo, TCG_CALL_NO_WG, void, env, i32, i64, i64)
> diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c
> index df082f5..990858e 100644
> --- a/target/s390x/mem_helper.c
> +++ b/target/s390x/mem_helper.c
> @@ -538,12 +538,17 @@ static inline void set_length(CPUS390XState *env, int reg, uint64_t length)
> }
>
> /* search string (c is byte to search, r2 is string, r1 end of string) */
> -uint64_t HELPER(srst)(CPUS390XState *env, uint64_t r0, uint64_t end,
> - uint64_t str)
> +uint64_t HELPER(srst)(CPUS390XState *env, uint64_t end, uint64_t str)
> {
> uintptr_t ra = GETPC();
> uint32_t len;
> - uint8_t v, c = r0;
> + uint8_t v, c = env->regs[0];
> +
> + /* Bits 32-55 must contain all 0. */
> + if (env->regs[0] & 0xffffff00u) {
> + cpu_restore_state(ENV_GET_CPU(env), ra);
> + program_interrupt(env, PGM_SPECIFICATION, 6);
> + }
>
> str = wrap_address(env, str);
> end = wrap_address(env, end);
> diff --git a/target/s390x/translate.c b/target/s390x/translate.c
> index f8989ec..4a860f1 100644
> --- a/target/s390x/translate.c
> +++ b/target/s390x/translate.c
> @@ -4256,7 +4256,7 @@ static ExitStatus op_stpq(DisasContext *s, DisasOps *o)
>
> static ExitStatus op_srst(DisasContext *s, DisasOps *o)
> {
> - gen_helper_srst(o->in1, cpu_env, regs[0], o->in1, o->in2);
> + gen_helper_srst(o->in1, cpu_env, o->in1, o->in2);
> set_cc_static(s);
> return_low128(o->in2);
> return NO_EXIT;
The cleanup is a good step, but I guess that should also be the moment
to improve the address masking/wrapping (see comment on next patch).
Anyway:
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 40+ messages in thread
* [Qemu-devel] [PATCH v3 15/18] target/s390x: Implement SRSTU
2017-06-20 0:03 [Qemu-devel] [PATCH v3 00/18] target/s390x improvements Richard Henderson
` (11 preceding siblings ...)
2017-06-20 0:04 ` [Qemu-devel] [PATCH v3 14/18] target/s390x: Tidy SRST Richard Henderson
@ 2017-06-20 0:04 ` Richard Henderson
2017-06-20 8:12 ` David Hildenbrand
2017-06-23 15:52 ` Aurelien Jarno
2017-06-20 0:04 ` [Qemu-devel] [PATCH v3 16/18] target/s390x: Implement TRTR Richard Henderson
` (5 subsequent siblings)
18 siblings, 2 replies; 40+ messages in thread
From: Richard Henderson @ 2017-06-20 0:04 UTC (permalink / raw)
To: qemu-devel; +Cc: thuth, aurelien
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target/s390x/helper.h | 1 +
target/s390x/insn-data.def | 2 ++
target/s390x/mem_helper.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
target/s390x/translate.c | 8 ++++++++
4 files changed, 55 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index cd51b89..58d7f5b 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -13,6 +13,7 @@ DEF_HELPER_FLAGS_3(divu32, TCG_CALL_NO_WG, i64, env, i64, i64)
DEF_HELPER_FLAGS_3(divs64, TCG_CALL_NO_WG, s64, env, s64, s64)
DEF_HELPER_FLAGS_4(divu64, TCG_CALL_NO_WG, i64, env, i64, i64, i64)
DEF_HELPER_3(srst, i64, env, i64, i64)
+DEF_HELPER_3(srstu, i64, env, i64, i64)
DEF_HELPER_4(clst, i64, env, i64, i64, i64)
DEF_HELPER_FLAGS_4(mvn, TCG_CALL_NO_WG, void, env, i32, i64, i64)
DEF_HELPER_FLAGS_4(mvo, TCG_CALL_NO_WG, void, env, i32, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 634ef98..1bebcf2 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -736,6 +736,8 @@
/* SEARCH STRING */
C(0xb25e, SRST, RRE, Z, r1_o, r2_o, 0, 0, srst, 0)
+/* SEARCH STRING UNICODE */
+ C(0xb9be, SRSTU, RRE, ETF3, r1_o, r2_o, 0, 0, srstu, 0)
/* SET ACCESS */
C(0xb24e, SAR, RRE, Z, 0, r2_o, 0, 0, sar, 0)
diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c
index 990858e..ce288d9 100644
--- a/target/s390x/mem_helper.c
+++ b/target/s390x/mem_helper.c
@@ -578,6 +578,50 @@ uint64_t HELPER(srst)(CPUS390XState *env, uint64_t end, uint64_t str)
return end;
}
+uint64_t HELPER(srstu)(CPUS390XState *env, uint64_t end, uint64_t str)
+{
+ uintptr_t ra = GETPC();
+ uint32_t len;
+ uint16_t v, c = env->regs[0];
+ uint64_t adj_end;
+
+ /* Bits 32-47 of R0 must be zero. */
+ if (env->regs[0] & 0xffff0000u) {
+ cpu_restore_state(ENV_GET_CPU(env), ra);
+ program_interrupt(env, PGM_SPECIFICATION, 6);
+ }
+
+ str = wrap_address(env, str);
+ end = wrap_address(env, end);
+
+ /* If the LSB of the two addresses differ, use one extra byte. */
+ adj_end = end + ((str ^ end) & 1);
+
+ /* Assume for now that R2 is unmodified. */
+ env->retxl = str;
+
+ /* Lest we fail to service interrupts in a timely manner, limit the
+ amount of work we're willing to do. For now, let's cap at 8k. */
+ for (len = 0; len < 0x2000; len += 2) {
+ if (str + len == adj_end) {
+ /* End of input found. */
+ env->cc_op = 2;
+ return end;
+ }
+ v = cpu_lduw_data_ra(env, str + len, ra);
+ if (v == c) {
+ /* Character found. Set R1 to the location; R2 is unmodified. */
+ env->cc_op = 1;
+ return str + len;
+ }
+ }
+
+ /* CPU-determined bytes processed. Advance R2 to next byte to process. */
+ env->retxl = str + len;
+ env->cc_op = 3;
+ return end;
+}
+
/* unsigned string compare (c is string terminator) */
uint64_t HELPER(clst)(CPUS390XState *env, uint64_t c, uint64_t s1, uint64_t s2)
{
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 4a860f1..e594b91 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -4262,6 +4262,14 @@ static ExitStatus op_srst(DisasContext *s, DisasOps *o)
return NO_EXIT;
}
+static ExitStatus op_srstu(DisasContext *s, DisasOps *o)
+{
+ gen_helper_srstu(o->in1, cpu_env, o->in1, o->in2);
+ set_cc_static(s);
+ return_low128(o->in2);
+ return NO_EXIT;
+}
+
static ExitStatus op_sub(DisasContext *s, DisasOps *o)
{
tcg_gen_sub_i64(o->out, o->in1, o->in2);
--
2.9.4
^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [Qemu-devel] [PATCH v3 15/18] target/s390x: Implement SRSTU
2017-06-20 0:04 ` [Qemu-devel] [PATCH v3 15/18] target/s390x: Implement SRSTU Richard Henderson
@ 2017-06-20 8:12 ` David Hildenbrand
2017-06-20 8:27 ` David Hildenbrand
2017-06-23 15:52 ` Aurelien Jarno
1 sibling, 1 reply; 40+ messages in thread
From: David Hildenbrand @ 2017-06-20 8:12 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: thuth, aurelien
> +uint64_t HELPER(srstu)(CPUS390XState *env, uint64_t end, uint64_t str)
> +{
> + uintptr_t ra = GETPC();
> + uint32_t len;
> + uint16_t v, c = env->regs[0];
> + uint64_t adj_end;
> +
> + /* Bits 32-47 of R0 must be zero. */
> + if (env->regs[0] & 0xffff0000u) {
> + cpu_restore_state(ENV_GET_CPU(env), ra);
> + program_interrupt(env, PGM_SPECIFICATION, 6);
> + }
> +
> + str = wrap_address(env, str);
> + end = wrap_address(env, end);
> +
> + /* If the LSB of the two addresses differ, use one extra byte. */
> + adj_end = end + ((str ^ end) & 1);
This could theoretically wrap. Not sure how this is to be handled, do you?
> +
> + /* Assume for now that R2 is unmodified. */
> + env->retxl = str;
If str was wrapped, r2 could be modified although it should not be touched.
> +
> + /* Lest we fail to service interrupts in a timely manner, limit the
> + amount of work we're willing to do. For now, let's cap at 8k. */
> + for (len = 0; len < 0x2000; len += 2) {
> + if (str + len == adj_end) {
> + /* End of input found. */
> + env->cc_op = 2;
> + return end;
If end was wrapped, r1 is modified here.
> + }
Also str + len could wrap here. Not sure how this is to be handled.
> + v = cpu_lduw_data_ra(env, str + len, ra);
> + if (v == c) {
> + /* Character found. Set R1 to the location; R2 is unmodified. */
> + env->cc_op = 1;
> + return str + len;
> + }
> + }
> +
> + /* CPU-determined bytes processed. Advance R2 to next byte to process. */
> + env->retxl = str + len;
Also wonder if r2 should be wrapped here. And if the "unused" bits
should be left unmodified here.
> + env->cc_op = 3;
> + return end;
Again, r1 could be modified here if end was wrapped.
> +}
> +
> /* unsigned string compare (c is string terminator) */
> uint64_t HELPER(clst)(CPUS390XState *env, uint64_t c, uint64_t s1, uint64_t s2)
> {
> diff --git a/target/s390x/translate.c b/target/s390x/translate.c
> index 4a860f1..e594b91 100644
> --- a/target/s390x/translate.c
> +++ b/target/s390x/translate.c
> @@ -4262,6 +4262,14 @@ static ExitStatus op_srst(DisasContext *s, DisasOps *o)
> return NO_EXIT;
> }
>
> +static ExitStatus op_srstu(DisasContext *s, DisasOps *o)
> +{
> + gen_helper_srstu(o->in1, cpu_env, o->in1, o->in2);
> + set_cc_static(s);
> + return_low128(o->in2);
> + return NO_EXIT;
> +}
> +
> static ExitStatus op_sub(DisasContext *s, DisasOps *o)
> {
> tcg_gen_sub_i64(o->out, o->in1, o->in2);
>
Apart from special wrapping conditions, looks good to me!
(will scan the PoP how wrapping is to be handled in general during an
instruction. Some (like mvcos) mention it explicitly, others don't)
--
Thanks,
David
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [Qemu-devel] [PATCH v3 15/18] target/s390x: Implement SRSTU
2017-06-20 8:12 ` David Hildenbrand
@ 2017-06-20 8:27 ` David Hildenbrand
2017-06-20 17:21 ` Richard Henderson
0 siblings, 1 reply; 40+ messages in thread
From: David Hildenbrand @ 2017-06-20 8:27 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: thuth, aurelien
> Apart from special wrapping conditions, looks good to me!
>
> (will scan the PoP how wrapping is to be handled in general during an
> instruction. Some (like mvcos) mention it explicitly, others don't)
>
Answering my own questions:
1. We always have to wrap addresses that we generate except in some
special cases:
(PoP page 3-7)
"
The CPU performs address generation when it forms
an operand or instruction address or when it gener-
ates the address of a table entry from the appropriate
table origin and index. It also performs address gen-
eration when it increments an address to access suc-
cessive bytes of a field.
When, during the generation of the address, an
address is obtained that exceeds the value allowed
[...] one of the following two actions is taken:
1. The carry out of the high-order bit position of the
address is ignored. This handling of an address
of excessive size is called wraparound.
2. An interruption condition is recognized.
[...]
Addresses generated by the CPU that may be virtual
addresses always wrap."
... reading the following table, interrupts seem to get generated only
for some iplicit DAT translations/AR-mode tables and authority tables,
and only when Real or Absolute addresses are to be used.
So wrapping all addresses is done in general when working with virtual
addresses, whenever we generate an address.
2. We must not overwrite bit 0-31 in 24/31 bit mode:
(PoP page 3-6)
Unless specifically stated to the contrary, the follow-
ing definition applies in this publication: whenever the
machine generates and provides to the program a
24-bit or 31-bit address, the address is made avail-
able (placed in storage or loaded into a general regis-
ter) by being imbedded in a 32-bit field, with the
leftmost eight bits or one bit in the field, respectively,
set to zeros. When the address is loaded into a gen-
eral register, bits 0-31 of the register remain
unchanged.
--
Thanks,
David
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [Qemu-devel] [PATCH v3 15/18] target/s390x: Implement SRSTU
2017-06-20 8:27 ` David Hildenbrand
@ 2017-06-20 17:21 ` Richard Henderson
0 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2017-06-20 17:21 UTC (permalink / raw)
To: David Hildenbrand, qemu-devel; +Cc: thuth, aurelien
On 06/20/2017 01:27 AM, David Hildenbrand wrote:
> 2. We must not overwrite bit 0-31 in 24/31 bit mode:
>
> (PoP page 3-6)
> Unless specifically stated to the contrary, the follow-
> ing definition applies in this publication: whenever the
> machine generates and provides to the program a
> 24-bit or 31-bit address, the address is made avail-
> able (placed in storage or loaded into a general regis-
> ter) by being imbedded in a 32-bit field, with the
> leftmost eight bits or one bit in the field, respectively,
> set to zeros. When the address is loaded into a gen-
> eral register, bits 0-31 of the register remain
> unchanged.
Yes, Aurelien started down these lines when he added the set_address/set_length
functions. We just need to use them more often, I suppose.
r~
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [Qemu-devel] [PATCH v3 15/18] target/s390x: Implement SRSTU
2017-06-20 0:04 ` [Qemu-devel] [PATCH v3 15/18] target/s390x: Implement SRSTU Richard Henderson
2017-06-20 8:12 ` David Hildenbrand
@ 2017-06-23 15:52 ` Aurelien Jarno
1 sibling, 0 replies; 40+ messages in thread
From: Aurelien Jarno @ 2017-06-23 15:52 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, thuth
On 2017-06-19 17:04, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target/s390x/helper.h | 1 +
> target/s390x/insn-data.def | 2 ++
> target/s390x/mem_helper.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
> target/s390x/translate.c | 8 ++++++++
> 4 files changed, 55 insertions(+)
>
> diff --git a/target/s390x/helper.h b/target/s390x/helper.h
> index cd51b89..58d7f5b 100644
> --- a/target/s390x/helper.h
> +++ b/target/s390x/helper.h
> @@ -13,6 +13,7 @@ DEF_HELPER_FLAGS_3(divu32, TCG_CALL_NO_WG, i64, env, i64, i64)
> DEF_HELPER_FLAGS_3(divs64, TCG_CALL_NO_WG, s64, env, s64, s64)
> DEF_HELPER_FLAGS_4(divu64, TCG_CALL_NO_WG, i64, env, i64, i64, i64)
> DEF_HELPER_3(srst, i64, env, i64, i64)
> +DEF_HELPER_3(srstu, i64, env, i64, i64)
> DEF_HELPER_4(clst, i64, env, i64, i64, i64)
> DEF_HELPER_FLAGS_4(mvn, TCG_CALL_NO_WG, void, env, i32, i64, i64)
> DEF_HELPER_FLAGS_4(mvo, TCG_CALL_NO_WG, void, env, i32, i64, i64)
> diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
> index 634ef98..1bebcf2 100644
> --- a/target/s390x/insn-data.def
> +++ b/target/s390x/insn-data.def
> @@ -736,6 +736,8 @@
>
> /* SEARCH STRING */
> C(0xb25e, SRST, RRE, Z, r1_o, r2_o, 0, 0, srst, 0)
> +/* SEARCH STRING UNICODE */
> + C(0xb9be, SRSTU, RRE, ETF3, r1_o, r2_o, 0, 0, srstu, 0)
>
> /* SET ACCESS */
> C(0xb24e, SAR, RRE, Z, 0, r2_o, 0, 0, sar, 0)
> diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c
> index 990858e..ce288d9 100644
> --- a/target/s390x/mem_helper.c
> +++ b/target/s390x/mem_helper.c
> @@ -578,6 +578,50 @@ uint64_t HELPER(srst)(CPUS390XState *env, uint64_t end, uint64_t str)
> return end;
> }
>
> +uint64_t HELPER(srstu)(CPUS390XState *env, uint64_t end, uint64_t str)
> +{
> + uintptr_t ra = GETPC();
> + uint32_t len;
> + uint16_t v, c = env->regs[0];
> + uint64_t adj_end;
> +
> + /* Bits 32-47 of R0 must be zero. */
> + if (env->regs[0] & 0xffff0000u) {
> + cpu_restore_state(ENV_GET_CPU(env), ra);
> + program_interrupt(env, PGM_SPECIFICATION, 6);
> + }
> +
> + str = wrap_address(env, str);
> + end = wrap_address(env, end);
> +
> + /* If the LSB of the two addresses differ, use one extra byte. */
> + adj_end = end + ((str ^ end) & 1);
> +
> + /* Assume for now that R2 is unmodified. */
> + env->retxl = str;
> +
> + /* Lest we fail to service interrupts in a timely manner, limit the
> + amount of work we're willing to do. For now, let's cap at 8k. */
> + for (len = 0; len < 0x2000; len += 2) {
> + if (str + len == adj_end) {
> + /* End of input found. */
> + env->cc_op = 2;
> + return end;
> + }
> + v = cpu_lduw_data_ra(env, str + len, ra);
> + if (v == c) {
> + /* Character found. Set R1 to the location; R2 is unmodified. */
> + env->cc_op = 1;
> + return str + len;
> + }
> + }
> +
> + /* CPU-determined bytes processed. Advance R2 to next byte to process. */
> + env->retxl = str + len;
> + env->cc_op = 3;
> + return end;
> +}
> +
> /* unsigned string compare (c is string terminator) */
> uint64_t HELPER(clst)(CPUS390XState *env, uint64_t c, uint64_t s1, uint64_t s2)
> {
Overall that looks fine, but I think we should get the wrapping (almost)
correct, now that we have the get_address / set_address functions. As
all registers are saved on input, I guess the registers can be directly
written back in the helper using set_address. It should handle most of
the cases, except wrapping at the end of the address space, but anyway
I don't think it's handled somewhere.
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 40+ messages in thread
* [Qemu-devel] [PATCH v3 16/18] target/s390x: Implement TRTR
2017-06-20 0:03 [Qemu-devel] [PATCH v3 00/18] target/s390x improvements Richard Henderson
` (12 preceding siblings ...)
2017-06-20 0:04 ` [Qemu-devel] [PATCH v3 15/18] target/s390x: Implement SRSTU Richard Henderson
@ 2017-06-20 0:04 ` Richard Henderson
2017-06-23 15:53 ` Aurelien Jarno
2017-06-20 0:04 ` [Qemu-devel] [PATCH v3 17/18] target/s390x: Mark ETF3 and ETF3_ENH facilities as available Richard Henderson
` (4 subsequent siblings)
18 siblings, 1 reply; 40+ messages in thread
From: Richard Henderson @ 2017-06-20 0:04 UTC (permalink / raw)
To: qemu-devel; +Cc: thuth, aurelien
Drop TRT from the set of insns handled internally by EXECUTE.
It's more important to adjust the existing helper to handle
both TRT and TRTR.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target/s390x/helper.h | 1 +
target/s390x/insn-data.def | 2 ++
target/s390x/mem_helper.c | 20 +++++++++++++-------
target/s390x/translate.c | 9 +++++++++
4 files changed, 25 insertions(+), 7 deletions(-)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 58d7f5b..61533b9 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -97,6 +97,7 @@ DEF_HELPER_FLAGS_3(tp, TCG_CALL_NO_WG, i32, env, i64, i32)
DEF_HELPER_FLAGS_4(tr, TCG_CALL_NO_WG, void, env, i32, i64, i64)
DEF_HELPER_4(tre, i64, env, i64, i64, i64)
DEF_HELPER_4(trt, i32, env, i32, i64, i64)
+DEF_HELPER_4(trtr, i32, env, i32, i64, i64)
DEF_HELPER_5(trXX, i32, env, i32, i32, i32, i32)
DEF_HELPER_4(cksm, i64, env, i64, i64, i64)
DEF_HELPER_FLAGS_5(calc_cc, TCG_CALL_NO_RWG_SE, i32, env, i32, i64, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 1bebcf2..7d558df 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -915,6 +915,8 @@
C(0xdc00, TR, SS_a, Z, la1, a2, 0, 0, tr, 0)
/* TRANSLATE AND TEST */
C(0xdd00, TRT, SS_a, Z, la1, a2, 0, 0, trt, 0)
+/* TRANSLATE AND TEST REVERSE */
+ C(0xd000, TRTR, SS_a, ETF3, la1, a2, 0, 0, trtr, 0)
/* TRANSLATE EXTENDED */
C(0xb2a5, TRE, RRE, Z, 0, r2, r1_P, 0, tre, 0)
diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c
index ce288d9..80926fa 100644
--- a/target/s390x/mem_helper.c
+++ b/target/s390x/mem_helper.c
@@ -1282,17 +1282,18 @@ uint64_t HELPER(tre)(CPUS390XState *env, uint64_t array,
return array + i;
}
-static uint32_t do_helper_trt(CPUS390XState *env, uint32_t len, uint64_t array,
- uint64_t trans, uintptr_t ra)
+static inline uint32_t do_helper_trt(CPUS390XState *env, int len,
+ uint64_t array, uint64_t trans,
+ int inc, uintptr_t ra)
{
- uint32_t i;
+ int i;
for (i = 0; i <= len; i++) {
- uint8_t byte = cpu_ldub_data_ra(env, array + i, ra);
+ uint8_t byte = cpu_ldub_data_ra(env, array + i * inc, ra);
uint8_t sbyte = cpu_ldub_data_ra(env, trans + byte, ra);
if (sbyte != 0) {
- set_address(env, 1, array + i);
+ set_address(env, 1, array + i * inc);
env->regs[2] = deposit64(env->regs[2], 0, 8, sbyte);
return (i == len) ? 2 : 1;
}
@@ -1304,7 +1305,13 @@ static uint32_t do_helper_trt(CPUS390XState *env, uint32_t len, uint64_t array,
uint32_t HELPER(trt)(CPUS390XState *env, uint32_t len, uint64_t array,
uint64_t trans)
{
- return do_helper_trt(env, len, array, trans, GETPC());
+ return do_helper_trt(env, len, array, trans, 1, GETPC());
+}
+
+uint32_t HELPER(trtr)(CPUS390XState *env, uint32_t len, uint64_t array,
+ uint64_t trans)
+{
+ return do_helper_trt(env, len, array, trans, -1, GETPC());
}
/* Translate one/two to one/two */
@@ -2068,7 +2075,6 @@ void HELPER(ex)(CPUS390XState *env, uint32_t ilen, uint64_t r1, uint64_t addr)
[0x6] = do_helper_oc,
[0x7] = do_helper_xc,
[0xc] = do_helper_tr,
- [0xd] = do_helper_trt,
};
dx_helper helper = dx[opc & 0xf];
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index e594b91..9893551 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -4406,6 +4406,15 @@ static ExitStatus op_trt(DisasContext *s, DisasOps *o)
return NO_EXIT;
}
+static ExitStatus op_trtr(DisasContext *s, DisasOps *o)
+{
+ TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
+ gen_helper_trtr(cc_op, cpu_env, l, o->addr1, o->in2);
+ tcg_temp_free_i32(l);
+ set_cc_static(s);
+ return NO_EXIT;
+}
+
static ExitStatus op_trXX(DisasContext *s, DisasOps *o)
{
TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
--
2.9.4
^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [Qemu-devel] [PATCH v3 16/18] target/s390x: Implement TRTR
2017-06-20 0:04 ` [Qemu-devel] [PATCH v3 16/18] target/s390x: Implement TRTR Richard Henderson
@ 2017-06-23 15:53 ` Aurelien Jarno
0 siblings, 0 replies; 40+ messages in thread
From: Aurelien Jarno @ 2017-06-23 15:53 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, thuth
On 2017-06-19 17:04, Richard Henderson wrote:
> Drop TRT from the set of insns handled internally by EXECUTE.
> It's more important to adjust the existing helper to handle
> both TRT and TRTR.
>
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target/s390x/helper.h | 1 +
> target/s390x/insn-data.def | 2 ++
> target/s390x/mem_helper.c | 20 +++++++++++++-------
> target/s390x/translate.c | 9 +++++++++
> 4 files changed, 25 insertions(+), 7 deletions(-)
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 40+ messages in thread
* [Qemu-devel] [PATCH v3 17/18] target/s390x: Mark ETF3 and ETF3_ENH facilities as available
2017-06-20 0:03 [Qemu-devel] [PATCH v3 00/18] target/s390x improvements Richard Henderson
` (13 preceding siblings ...)
2017-06-20 0:04 ` [Qemu-devel] [PATCH v3 16/18] target/s390x: Implement TRTR Richard Henderson
@ 2017-06-20 0:04 ` Richard Henderson
2017-06-23 15:53 ` Aurelien Jarno
2017-06-20 0:04 ` [Qemu-devel] [PATCH v3 18/18] target/s390x: Clean up TB flag bits Richard Henderson
` (3 subsequent siblings)
18 siblings, 1 reply; 40+ messages in thread
From: Richard Henderson @ 2017-06-20 0:04 UTC (permalink / raw)
To: qemu-devel; +Cc: thuth, aurelien
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target/s390x/cpu_models.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c
index be7757c..16129f6 100644
--- a/target/s390x/cpu_models.c
+++ b/target/s390x/cpu_models.c
@@ -678,11 +678,13 @@ static void add_qemu_cpu_model_features(S390FeatBitmap fbm)
S390_FEAT_STFLE,
S390_FEAT_EXTENDED_IMMEDIATE,
S390_FEAT_EXTENDED_TRANSLATION_2,
+ S390_FEAT_EXTENDED_TRANSLATION_3,
S390_FEAT_LONG_DISPLACEMENT,
S390_FEAT_LONG_DISPLACEMENT_FAST,
S390_FEAT_ETF2_ENH,
S390_FEAT_STORE_CLOCK_FAST,
S390_FEAT_MOVE_WITH_OPTIONAL_SPEC,
+ S390_FEAT_ETF3_ENH,
S390_FEAT_COMPARE_AND_SWAP_AND_STORE,
S390_FEAT_COMPARE_AND_SWAP_AND_STORE_2,
S390_FEAT_GENERAL_INSTRUCTIONS_EXT,
--
2.9.4
^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [Qemu-devel] [PATCH v3 17/18] target/s390x: Mark ETF3 and ETF3_ENH facilities as available
2017-06-20 0:04 ` [Qemu-devel] [PATCH v3 17/18] target/s390x: Mark ETF3 and ETF3_ENH facilities as available Richard Henderson
@ 2017-06-23 15:53 ` Aurelien Jarno
0 siblings, 0 replies; 40+ messages in thread
From: Aurelien Jarno @ 2017-06-23 15:53 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, thuth
On 2017-06-19 17:04, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target/s390x/cpu_models.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c
> index be7757c..16129f6 100644
> --- a/target/s390x/cpu_models.c
> +++ b/target/s390x/cpu_models.c
> @@ -678,11 +678,13 @@ static void add_qemu_cpu_model_features(S390FeatBitmap fbm)
> S390_FEAT_STFLE,
> S390_FEAT_EXTENDED_IMMEDIATE,
> S390_FEAT_EXTENDED_TRANSLATION_2,
> + S390_FEAT_EXTENDED_TRANSLATION_3,
> S390_FEAT_LONG_DISPLACEMENT,
> S390_FEAT_LONG_DISPLACEMENT_FAST,
> S390_FEAT_ETF2_ENH,
> S390_FEAT_STORE_CLOCK_FAST,
> S390_FEAT_MOVE_WITH_OPTIONAL_SPEC,
> + S390_FEAT_ETF3_ENH,
> S390_FEAT_COMPARE_AND_SWAP_AND_STORE,
> S390_FEAT_COMPARE_AND_SWAP_AND_STORE_2,
> S390_FEAT_GENERAL_INSTRUCTIONS_EXT,
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 40+ messages in thread
* [Qemu-devel] [PATCH v3 18/18] target/s390x: Clean up TB flag bits
2017-06-20 0:03 [Qemu-devel] [PATCH v3 00/18] target/s390x improvements Richard Henderson
` (14 preceding siblings ...)
2017-06-20 0:04 ` [Qemu-devel] [PATCH v3 17/18] target/s390x: Mark ETF3 and ETF3_ENH facilities as available Richard Henderson
@ 2017-06-20 0:04 ` Richard Henderson
2017-06-20 3:16 ` Philippe Mathieu-Daudé
2017-06-23 15:53 ` Aurelien Jarno
[not found] ` <20170620000405.3391-8-rth@twiddle.net>
` (2 subsequent siblings)
18 siblings, 2 replies; 40+ messages in thread
From: Richard Henderson @ 2017-06-20 0:04 UTC (permalink / raw)
To: qemu-devel; +Cc: thuth, aurelien
Most of the PSW bits that were being copied into TB->flags
are not relevant to translation. Removing those that are
unnecessary reduces the amount of translation required.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target/s390x/cpu.h | 24 +++++++++---------------
target/s390x/translate.c | 16 ++++++++--------
2 files changed, 17 insertions(+), 23 deletions(-)
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 5b94ace..9faca04 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -346,19 +346,14 @@ void s390x_cpu_debug_excp_handler(CPUState *cs);
/* tb flags */
-#define FLAG_MASK_PER (PSW_MASK_PER >> 32)
-#define FLAG_MASK_DAT (PSW_MASK_DAT >> 32)
-#define FLAG_MASK_IO (PSW_MASK_IO >> 32)
-#define FLAG_MASK_EXT (PSW_MASK_EXT >> 32)
-#define FLAG_MASK_KEY (PSW_MASK_KEY >> 32)
-#define FLAG_MASK_MCHECK (PSW_MASK_MCHECK >> 32)
-#define FLAG_MASK_WAIT (PSW_MASK_WAIT >> 32)
-#define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> 32)
-#define FLAG_MASK_ASC (PSW_MASK_ASC >> 32)
-#define FLAG_MASK_CC (PSW_MASK_CC >> 32)
-#define FLAG_MASK_PM (PSW_MASK_PM >> 32)
-#define FLAG_MASK_64 (PSW_MASK_64 >> 32)
-#define FLAG_MASK_32 0x00001000
+#define FLAG_MASK_PSW_SHIFT 31
+#define FLAG_MASK_PER (PSW_MASK_PER >> FLAG_MASK_PSW_SHIFT)
+#define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT)
+#define FLAG_MASK_ASC (PSW_MASK_ASC >> FLAG_MASK_PSW_SHIFT)
+#define FLAG_MASK_64 (PSW_MASK_64 >> FLAG_MASK_PSW_SHIFT)
+#define FLAG_MASK_32 (PSW_MASK_32 >> FLAG_MASK_PSW_SHIFT)
+#define FLAG_MASK_PSW (FLAG_MASK_PER | FLAG_MASK_PSTATE \
+ | FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32)
/* Control register 0 bits */
#define CR0_LOWPROT 0x0000000010000000ULL
@@ -416,8 +411,7 @@ static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
{
*pc = env->psw.addr;
*cs_base = env->ex_value;
- *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
- ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
+ *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW;
}
#define MAX_ILEN 6
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 9893551..bee163f 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -323,11 +323,11 @@ static inline uint64_t ld_code4(CPUS390XState *env, uint64_t pc)
static int get_mem_index(DisasContext *s)
{
switch (s->tb->flags & FLAG_MASK_ASC) {
- case PSW_ASC_PRIMARY >> 32:
+ case PSW_ASC_PRIMARY >> FLAG_MASK_PSW_SHIFT:
return 0;
- case PSW_ASC_SECONDARY >> 32:
+ case PSW_ASC_SECONDARY >> FLAG_MASK_PSW_SHIFT:
return 1;
- case PSW_ASC_HOME >> 32:
+ case PSW_ASC_HOME >> FLAG_MASK_PSW_SHIFT:
return 2;
default:
tcg_abort();
@@ -387,7 +387,7 @@ static inline void gen_trap(DisasContext *s)
#ifndef CONFIG_USER_ONLY
static void check_privileged(DisasContext *s)
{
- if (s->tb->flags & (PSW_MASK_PSTATE >> 32)) {
+ if (s->tb->flags & FLAG_MASK_PSTATE) {
gen_program_exception(s, PGM_PRIVILEGED);
}
}
@@ -2985,20 +2985,20 @@ static ExitStatus op_mov2e(DisasContext *s, DisasOps *o)
o->g_in2 = false;
switch (s->tb->flags & FLAG_MASK_ASC) {
- case PSW_ASC_PRIMARY >> 32:
+ case PSW_ASC_PRIMARY >> FLAG_MASK_PSW_SHIFT:
tcg_gen_movi_i64(ar1, 0);
break;
- case PSW_ASC_ACCREG >> 32:
+ case PSW_ASC_ACCREG >> FLAG_MASK_PSW_SHIFT:
tcg_gen_movi_i64(ar1, 1);
break;
- case PSW_ASC_SECONDARY >> 32:
+ case PSW_ASC_SECONDARY >> FLAG_MASK_PSW_SHIFT:
if (b2) {
tcg_gen_ld32u_i64(ar1, cpu_env, offsetof(CPUS390XState, aregs[b2]));
} else {
tcg_gen_movi_i64(ar1, 0);
}
break;
- case PSW_ASC_HOME >> 32:
+ case PSW_ASC_HOME >> FLAG_MASK_PSW_SHIFT:
tcg_gen_movi_i64(ar1, 2);
break;
}
--
2.9.4
^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [Qemu-devel] [PATCH v3 18/18] target/s390x: Clean up TB flag bits
2017-06-20 0:04 ` [Qemu-devel] [PATCH v3 18/18] target/s390x: Clean up TB flag bits Richard Henderson
@ 2017-06-20 3:16 ` Philippe Mathieu-Daudé
2017-06-23 15:53 ` Aurelien Jarno
1 sibling, 0 replies; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2017-06-20 3:16 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: thuth, aurelien
On 06/19/2017 09:04 PM, Richard Henderson wrote:
> Most of the PSW bits that were being copied into TB->flags
> are not relevant to translation. Removing those that are
> unnecessary reduces the amount of translation required.
>
> Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/s390x/cpu.h | 24 +++++++++---------------
> target/s390x/translate.c | 16 ++++++++--------
> 2 files changed, 17 insertions(+), 23 deletions(-)
>
> diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
> index 5b94ace..9faca04 100644
> --- a/target/s390x/cpu.h
> +++ b/target/s390x/cpu.h
> @@ -346,19 +346,14 @@ void s390x_cpu_debug_excp_handler(CPUState *cs);
>
> /* tb flags */
>
> -#define FLAG_MASK_PER (PSW_MASK_PER >> 32)
> -#define FLAG_MASK_DAT (PSW_MASK_DAT >> 32)
> -#define FLAG_MASK_IO (PSW_MASK_IO >> 32)
> -#define FLAG_MASK_EXT (PSW_MASK_EXT >> 32)
> -#define FLAG_MASK_KEY (PSW_MASK_KEY >> 32)
> -#define FLAG_MASK_MCHECK (PSW_MASK_MCHECK >> 32)
> -#define FLAG_MASK_WAIT (PSW_MASK_WAIT >> 32)
> -#define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> 32)
> -#define FLAG_MASK_ASC (PSW_MASK_ASC >> 32)
> -#define FLAG_MASK_CC (PSW_MASK_CC >> 32)
> -#define FLAG_MASK_PM (PSW_MASK_PM >> 32)
> -#define FLAG_MASK_64 (PSW_MASK_64 >> 32)
> -#define FLAG_MASK_32 0x00001000
> +#define FLAG_MASK_PSW_SHIFT 31
> +#define FLAG_MASK_PER (PSW_MASK_PER >> FLAG_MASK_PSW_SHIFT)
> +#define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT)
> +#define FLAG_MASK_ASC (PSW_MASK_ASC >> FLAG_MASK_PSW_SHIFT)
> +#define FLAG_MASK_64 (PSW_MASK_64 >> FLAG_MASK_PSW_SHIFT)
> +#define FLAG_MASK_32 (PSW_MASK_32 >> FLAG_MASK_PSW_SHIFT)
> +#define FLAG_MASK_PSW (FLAG_MASK_PER | FLAG_MASK_PSTATE \
> + | FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32)
>
> /* Control register 0 bits */
> #define CR0_LOWPROT 0x0000000010000000ULL
> @@ -416,8 +411,7 @@ static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
> {
> *pc = env->psw.addr;
> *cs_base = env->ex_value;
> - *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
> - ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
> + *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW;
> }
>
> #define MAX_ILEN 6
> diff --git a/target/s390x/translate.c b/target/s390x/translate.c
> index 9893551..bee163f 100644
> --- a/target/s390x/translate.c
> +++ b/target/s390x/translate.c
> @@ -323,11 +323,11 @@ static inline uint64_t ld_code4(CPUS390XState *env, uint64_t pc)
> static int get_mem_index(DisasContext *s)
> {
> switch (s->tb->flags & FLAG_MASK_ASC) {
> - case PSW_ASC_PRIMARY >> 32:
> + case PSW_ASC_PRIMARY >> FLAG_MASK_PSW_SHIFT:
> return 0;
> - case PSW_ASC_SECONDARY >> 32:
> + case PSW_ASC_SECONDARY >> FLAG_MASK_PSW_SHIFT:
> return 1;
> - case PSW_ASC_HOME >> 32:
> + case PSW_ASC_HOME >> FLAG_MASK_PSW_SHIFT:
> return 2;
> default:
> tcg_abort();
> @@ -387,7 +387,7 @@ static inline void gen_trap(DisasContext *s)
> #ifndef CONFIG_USER_ONLY
> static void check_privileged(DisasContext *s)
> {
> - if (s->tb->flags & (PSW_MASK_PSTATE >> 32)) {
> + if (s->tb->flags & FLAG_MASK_PSTATE) {
> gen_program_exception(s, PGM_PRIVILEGED);
> }
> }
> @@ -2985,20 +2985,20 @@ static ExitStatus op_mov2e(DisasContext *s, DisasOps *o)
> o->g_in2 = false;
>
> switch (s->tb->flags & FLAG_MASK_ASC) {
> - case PSW_ASC_PRIMARY >> 32:
> + case PSW_ASC_PRIMARY >> FLAG_MASK_PSW_SHIFT:
> tcg_gen_movi_i64(ar1, 0);
> break;
> - case PSW_ASC_ACCREG >> 32:
> + case PSW_ASC_ACCREG >> FLAG_MASK_PSW_SHIFT:
> tcg_gen_movi_i64(ar1, 1);
> break;
> - case PSW_ASC_SECONDARY >> 32:
> + case PSW_ASC_SECONDARY >> FLAG_MASK_PSW_SHIFT:
> if (b2) {
> tcg_gen_ld32u_i64(ar1, cpu_env, offsetof(CPUS390XState, aregs[b2]));
> } else {
> tcg_gen_movi_i64(ar1, 0);
> }
> break;
> - case PSW_ASC_HOME >> 32:
> + case PSW_ASC_HOME >> FLAG_MASK_PSW_SHIFT:
> tcg_gen_movi_i64(ar1, 2);
> break;
> }
>
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [Qemu-devel] [PATCH v3 18/18] target/s390x: Clean up TB flag bits
2017-06-20 0:04 ` [Qemu-devel] [PATCH v3 18/18] target/s390x: Clean up TB flag bits Richard Henderson
2017-06-20 3:16 ` Philippe Mathieu-Daudé
@ 2017-06-23 15:53 ` Aurelien Jarno
1 sibling, 0 replies; 40+ messages in thread
From: Aurelien Jarno @ 2017-06-23 15:53 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, thuth
On 2017-06-19 17:04, Richard Henderson wrote:
> Most of the PSW bits that were being copied into TB->flags
> are not relevant to translation. Removing those that are
> unnecessary reduces the amount of translation required.
>
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target/s390x/cpu.h | 24 +++++++++---------------
> target/s390x/translate.c | 16 ++++++++--------
> 2 files changed, 17 insertions(+), 23 deletions(-)
>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 40+ messages in thread
[parent not found: <20170620000405.3391-8-rth@twiddle.net>]
* Re: [Qemu-devel] [PATCH v3 07/18] target/s390x: Implement load-and-zero-rightmost-byte insns
[not found] ` <20170620000405.3391-8-rth@twiddle.net>
@ 2017-06-23 11:01 ` Aurelien Jarno
0 siblings, 0 replies; 40+ messages in thread
From: Aurelien Jarno @ 2017-06-23 11:01 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, thuth
On 2017-06-19 17:03, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target/s390x/insn-data.def | 4 ++++
> target/s390x/translate.c | 7 +++++++
> 2 files changed, 11 insertions(+)
>
> diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
> index 60d244f..20dec56 100644
> --- a/target/s390x/insn-data.def
> +++ b/target/s390x/insn-data.def
> @@ -429,6 +429,10 @@
> /* LOAD AND TRAP */
> C(0xe39f, LAT, RXY_a, LAT, 0, m2_32u, r1, 0, lat, 0)
> C(0xe385, LGAT, RXY_a, LAT, 0, a2, r1, 0, lgat, 0)
> +/* LOAD AND ZERO RIGHTMOST BYTE */
> + C(0xe3eb, LZRF, RXY_a, LZRB, 0, m2_32u, new, r1_32, lzrb, 0)
> + C(0xe32a, LZRG, RXY_a, LZRB, 0, m2_64, r1, 0, lzrb, 0)
> + C(0xe33a, LLZRGF, RXY_a, LZRB, 0, m2_32u, r1, 0, lzrb, 0)
Small nitpick, LLZRGF is considered a separate instruction in the PoO,
called LOAD LOGICAL AND ZERO RIGHTMOST BYTE.
That said:
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 40+ messages in thread
[parent not found: <20170620000405.3391-10-rth@twiddle.net>]
* Re: [Qemu-devel] [PATCH v3 00/18] target/s390x improvements
2017-06-20 0:03 [Qemu-devel] [PATCH v3 00/18] target/s390x improvements Richard Henderson
` (17 preceding siblings ...)
[not found] ` <20170620000405.3391-10-rth@twiddle.net>
@ 2017-06-23 16:05 ` Aurelien Jarno
2017-06-27 15:54 ` David Hildenbrand
18 siblings, 1 reply; 40+ messages in thread
From: Aurelien Jarno @ 2017-06-23 16:05 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, thuth
On 2017-06-19 17:03, Richard Henderson wrote:
> Changes since v2:
> * Dropped the enforcement of PGM_OPERATION for insns for
> which the feature bit is set. There's no agreement on
> exactly how to do this yet.
> * Add implementations of insns for 6 more facilities.
>
> I think we can get to z990 fairly quickly after this.
> Ignoring HFP, the ones I see missing are DAT-ENH, MSA.
Thanks for this work. For the record I have started working on HFP
sometimes ago. I'll try to finish that and submit patches in the next
weeks.
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [Qemu-devel] [PATCH v3 00/18] target/s390x improvements
2017-06-23 16:05 ` [Qemu-devel] [PATCH v3 00/18] target/s390x improvements Aurelien Jarno
@ 2017-06-27 15:54 ` David Hildenbrand
0 siblings, 0 replies; 40+ messages in thread
From: David Hildenbrand @ 2017-06-27 15:54 UTC (permalink / raw)
To: Aurelien Jarno, Richard Henderson; +Cc: thuth, qemu-devel
On 23.06.2017 18:05, Aurelien Jarno wrote:
> On 2017-06-19 17:03, Richard Henderson wrote:
>> Changes since v2:
>> * Dropped the enforcement of PGM_OPERATION for insns for
>> which the feature bit is set. There's no agreement on
>> exactly how to do this yet.
>> * Add implementations of insns for 6 more facilities.
>>
>> I think we can get to z990 fairly quickly after this.
>> Ignoring HFP, the ones I see missing are DAT-ENH, MSA.
>
> Thanks for this work. For the record I have started working on HFP
> sometimes ago. I'll try to finish that and submit patches in the next
> weeks.
>
Just for the records, I am currently looking into MSA (at least
providing the functions (KM,KMC,KIMD ...) with only the query
subfunction), and I'll be looking into booting a z196 compiled linux
kernel under tcg.
--
Thanks,
David
^ permalink raw reply [flat|nested] 40+ messages in thread