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From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
	qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
	bmeng@tinylab.org, liweiwei@iscas.ac.cn, palmer@rivosinc.com
Subject: Re: [PATCH v3 4/6] target/riscv/tcg: add MISA user options hash
Date: Wed, 25 Oct 2023 14:45:12 +0800	[thread overview]
Message-ID: <f7a8038c-6ecb-451e-a7ba-bc81ff0bbe05@linux.alibaba.com> (raw)
In-Reply-To: <20231020223951.357513-5-dbarboza@ventanamicro.com>


On 2023/10/21 6:39, Daniel Henrique Barboza wrote:
> We already track user choice for multi-letter extensions because we
> needed to honor user choice when enabling/disabling extensions during
> realize(). We refrained from adding the same mechanism for MISA
> extensions since we didn't need it.
>
> Profile support requires tne need to check for user choice for MISA
> extensions, so let's add the corresponding hash now. It works like the
> existing multi-letter hash (multi_ext_user_opts) but tracking MISA bits
> options in the cpu_set_misa_ext_cfg() callback.
>
> Note that we can't re-use the same hash from multi-letter extensions
> because that hash uses cpu->cfg offsets as keys, while for MISA
> extensions we're using MISA bits as keys.
>
> After adding the user hash in cpu_set_misa_ext_cfg(), setting default
> values with object_property_set_bool() in add_misa_properties() will end
> up marking the user choice hash with them. Set the default value
> manually to avoid it.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>   target/riscv/tcg/tcg-cpu.c | 15 ++++++++++++++-
>   1 file changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 3dd4783191..59b75a14ac 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -34,6 +34,7 @@
>   
>   /* Hash that stores user set extensions */
>   static GHashTable *multi_ext_user_opts;
> +static GHashTable *misa_ext_user_opts;
>   
>   static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
>   {
> @@ -669,6 +670,10 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
>           return;
>       }
>   
> +    g_hash_table_insert(misa_ext_user_opts,
> +                        GUINT_TO_POINTER(misa_bit),
> +                        (gpointer)value);
> +
>       prev_val = env->misa_ext & misa_bit;
>   
>       if (value == prev_val) {
> @@ -732,6 +737,7 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
>    */
>   static void riscv_cpu_add_misa_properties(Object *cpu_obj)
>   {
> +    CPURISCVState *env = &RISCV_CPU(cpu_obj)->env;
>       bool use_def_vals = riscv_cpu_is_generic(cpu_obj);
>       int i;
>   
> @@ -752,7 +758,13 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
>                               NULL, (void *)misa_cfg);
>           object_property_set_description(cpu_obj, name, desc);
>           if (use_def_vals) {
> -            object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL);
> +            if (misa_cfg->enabled) {
> +                env->misa_ext |= bit;
> +                env->misa_ext_mask |= bit;
> +            } else {
> +                env->misa_ext &= ~bit;
> +                env->misa_ext_mask &= ~bit;
> +            }
>           }
>       }
>   }
> @@ -989,6 +1001,7 @@ static void tcg_cpu_instance_init(CPUState *cs)
>       RISCVCPU *cpu = RISCV_CPU(cs);
>       Object *obj = OBJECT(cpu);
>   
> +    misa_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);

Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>

Zhiwei

>       multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
>       riscv_cpu_add_user_properties(obj);
>   


  reply	other threads:[~2023-10-25  6:47 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-20 22:39 [PATCH v3 0/6] riscv: RVA22U64 profile support Daniel Henrique Barboza
2023-10-20 22:39 ` [PATCH v3 1/6] target/riscv: add rva22u64 profile definition Daniel Henrique Barboza
2023-10-25  6:22   ` LIU Zhiwei
2023-10-25 13:14     ` Daniel Henrique Barboza
2023-10-20 22:39 ` [PATCH v3 2/6] target/riscv/kvm: add 'rva22u64' flag as unavailable Daniel Henrique Barboza
2023-10-25  6:28   ` LIU Zhiwei
2023-10-20 22:39 ` [PATCH v3 3/6] target/riscv/tcg: add user flag for profile support Daniel Henrique Barboza
2023-10-23  8:16   ` Andrew Jones
2023-10-23 17:00     ` Daniel Henrique Barboza
2023-10-23 17:35       ` Andrew Jones
2023-10-23 17:54         ` Daniel Henrique Barboza
2023-10-26 14:36         ` Andrea Bolognani
2023-10-26 15:14           ` Andrew Jones
2023-10-26 17:36             ` Andrea Bolognani
2023-10-27 17:52               ` Daniel Henrique Barboza
2023-10-28  9:31                 ` Andrew Jones
2023-10-25  6:35   ` LIU Zhiwei
2023-10-20 22:39 ` [PATCH v3 4/6] target/riscv/tcg: add MISA user options hash Daniel Henrique Barboza
2023-10-25  6:45   ` LIU Zhiwei [this message]
2023-10-20 22:39 ` [PATCH v3 5/6] target/riscv/tcg: add riscv_cpu_write_misa_bit() Daniel Henrique Barboza
2023-10-25  6:45   ` LIU Zhiwei
2023-10-20 22:39 ` [PATCH v3 6/6] target/riscv/tcg: handle profile MISA bits Daniel Henrique Barboza
2023-10-25  6:46   ` LIU Zhiwei

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