* [PATCH v2 0/7] tcg/mips: Remove support for 32-bit hosts
@ 2025-10-09 19:52 Philippe Mathieu-Daudé
2025-10-09 19:52 ` [PATCH v2 1/7] docker: Remove 32-bit MIPS toolchain from debian-all-test image Philippe Mathieu-Daudé
` (6 more replies)
0 siblings, 7 replies; 14+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-09 19:52 UTC (permalink / raw)
To: qemu-devel
Cc: Alex Bennée, Thomas Huth, Paolo Bonzini, Richard Henderson,
Marc-André Lureau, Philippe Mathieu-Daudé, devel,
Jiaxun Yang, Aleksandar Rikalo, Riku Voipio,
Daniel P. Berrangé, Huacai Chen, Aurelien Jarno
Since v1:
- Removed N32/O32 ABIs (rth)
- Do not remove tgen_qemu_ld2/st2
32-bit hosts are deprecated since v10.0. 2 releases later (as
of v10.2) we can remove such code. Start with MIPS TCG backend.
Remove related buildsys and testing.
Philippe Mathieu-Daudé (7):
docker: Remove 32-bit MIPS toolchain from debian-all-test image
gitlab: Stop cross-testing for 32-bit MIPS hosts
docker: Stop building 32-bit MIPS images
tcg/mips: Remove support for O32 and N32 ABIs
tcg/mips: Remove support for 32-bit hosts
kvm/mips: Remove support for 32-bit hosts
buildsys: Remove support for 32-bit MIPS hosts
docs/about/deprecated.rst | 13 +-
docs/about/removed-features.rst | 6 +
configure | 9 -
meson.build | 2 -
tcg/mips/tcg-target-has.h | 2 -
tcg/mips/tcg-target-reg-bits.h | 9 +-
tcg/mips/tcg-target.c.inc | 292 +++---------------
.gitlab-ci.d/container-cross.yml | 6 -
.gitlab-ci.d/crossbuilds.yml | 14 -
common-user/host/mips/safe-syscall.inc.S | 35 ---
tests/docker/Makefile.include | 2 +-
.../dockerfiles/debian-all-test-cross.docker | 4 -
.../dockerfiles/debian-mipsel-cross.docker | 187 -----------
tests/lcitool/refresh | 5 -
14 files changed, 56 insertions(+), 530 deletions(-)
delete mode 100644 tests/docker/dockerfiles/debian-mipsel-cross.docker
--
2.51.0
^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH v2 1/7] docker: Remove 32-bit MIPS toolchain from debian-all-test image 2025-10-09 19:52 [PATCH v2 0/7] tcg/mips: Remove support for 32-bit hosts Philippe Mathieu-Daudé @ 2025-10-09 19:52 ` Philippe Mathieu-Daudé 2025-10-09 19:52 ` [PATCH v2 2/7] gitlab: Stop cross-testing for 32-bit MIPS hosts Philippe Mathieu-Daudé ` (5 subsequent siblings) 6 siblings, 0 replies; 14+ messages in thread From: Philippe Mathieu-Daudé @ 2025-10-09 19:52 UTC (permalink / raw) To: qemu-devel Cc: Alex Bennée, Thomas Huth, Paolo Bonzini, Richard Henderson, Marc-André Lureau, Philippe Mathieu-Daudé, devel, Jiaxun Yang, Aleksandar Rikalo, Riku Voipio, Daniel P. Berrangé, Huacai Chen, Aurelien Jarno In commit d3322023bfe ("configure: unify again the case arms in probe_target_compiler") we lost coverage of 32-bit MIPS with the debian-all-test image. No need to keep installing the toolchain. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> --- tests/docker/dockerfiles/debian-all-test-cross.docker | 4 ---- 1 file changed, 4 deletions(-) diff --git a/tests/docker/dockerfiles/debian-all-test-cross.docker b/tests/docker/dockerfiles/debian-all-test-cross.docker index 420a4e33e60..bc74d65a634 100644 --- a/tests/docker/dockerfiles/debian-all-test-cross.docker +++ b/tests/docker/dockerfiles/debian-all-test-cross.docker @@ -40,14 +40,10 @@ ENV AVAILABLE_COMPILERS gcc-aarch64-linux-gnu \ libc6-dev-arm64-cross \ gcc-arm-linux-gnueabihf \ libc6-dev-armhf-cross \ - gcc-mips-linux-gnu \ - libc6-dev-mips-cross \ gcc-mips64-linux-gnuabi64 \ libc6-dev-mips64-cross \ gcc-mips64el-linux-gnuabi64 \ libc6-dev-mips64el-cross \ - gcc-mipsel-linux-gnu \ - libc6-dev-mipsel-cross \ gcc-powerpc64le-linux-gnu \ libc6-dev-ppc64el-cross \ gcc-riscv64-linux-gnu \ -- 2.51.0 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 2/7] gitlab: Stop cross-testing for 32-bit MIPS hosts 2025-10-09 19:52 [PATCH v2 0/7] tcg/mips: Remove support for 32-bit hosts Philippe Mathieu-Daudé 2025-10-09 19:52 ` [PATCH v2 1/7] docker: Remove 32-bit MIPS toolchain from debian-all-test image Philippe Mathieu-Daudé @ 2025-10-09 19:52 ` Philippe Mathieu-Daudé 2025-10-09 19:52 ` [PATCH v2 3/7] docker: Stop building 32-bit MIPS images Philippe Mathieu-Daudé ` (4 subsequent siblings) 6 siblings, 0 replies; 14+ messages in thread From: Philippe Mathieu-Daudé @ 2025-10-09 19:52 UTC (permalink / raw) To: qemu-devel Cc: Alex Bennée, Thomas Huth, Paolo Bonzini, Richard Henderson, Marc-André Lureau, Philippe Mathieu-Daudé, devel, Jiaxun Yang, Aleksandar Rikalo, Riku Voipio, Daniel P. Berrangé, Huacai Chen, Aurelien Jarno 32-bit host support is deprecated since commit 6d701c9bac1 ("meson: Deprecate 32-bit host support"). Next commits will remove support for 32-bit MIPS hosts. Stop cross-building QEMU on our CI. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> --- .gitlab-ci.d/container-cross.yml | 6 ------ .gitlab-ci.d/crossbuilds.yml | 14 -------------- 2 files changed, 20 deletions(-) diff --git a/.gitlab-ci.d/container-cross.yml b/.gitlab-ci.d/container-cross.yml index 8d3be53b75b..0fd7341afac 100644 --- a/.gitlab-ci.d/container-cross.yml +++ b/.gitlab-ci.d/container-cross.yml @@ -52,12 +52,6 @@ mips64el-debian-cross-container: variables: NAME: debian-mips64el-cross -mipsel-debian-cross-container: - extends: .container_job_template - stage: containers - variables: - NAME: debian-mipsel-cross - ppc64el-debian-cross-container: extends: .container_job_template stage: containers diff --git a/.gitlab-ci.d/crossbuilds.yml b/.gitlab-ci.d/crossbuilds.yml index 8ff0c27f74d..99dfa7eea6f 100644 --- a/.gitlab-ci.d/crossbuilds.yml +++ b/.gitlab-ci.d/crossbuilds.yml @@ -68,20 +68,6 @@ cross-i686-tci: # would otherwise be using a parallelism of 9. MAKE_CHECK_ARGS: check check-tcg -j2 -cross-mipsel-system: - extends: .cross_system_build_job - needs: - - job: mipsel-debian-cross-container - variables: - IMAGE: debian-mipsel-cross - -cross-mipsel-user: - extends: .cross_user_build_job - needs: - - job: mipsel-debian-cross-container - variables: - IMAGE: debian-mipsel-cross - cross-mips64el-system: extends: .cross_system_build_job needs: -- 2.51.0 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 3/7] docker: Stop building 32-bit MIPS images 2025-10-09 19:52 [PATCH v2 0/7] tcg/mips: Remove support for 32-bit hosts Philippe Mathieu-Daudé 2025-10-09 19:52 ` [PATCH v2 1/7] docker: Remove 32-bit MIPS toolchain from debian-all-test image Philippe Mathieu-Daudé 2025-10-09 19:52 ` [PATCH v2 2/7] gitlab: Stop cross-testing for 32-bit MIPS hosts Philippe Mathieu-Daudé @ 2025-10-09 19:52 ` Philippe Mathieu-Daudé 2025-10-09 19:52 ` [PATCH v2 4/7] tcg/mips: Remove support for O32 and N32 ABIs Philippe Mathieu-Daudé ` (3 subsequent siblings) 6 siblings, 0 replies; 14+ messages in thread From: Philippe Mathieu-Daudé @ 2025-10-09 19:52 UTC (permalink / raw) To: qemu-devel Cc: Alex Bennée, Thomas Huth, Paolo Bonzini, Richard Henderson, Marc-André Lureau, Philippe Mathieu-Daudé, devel, Jiaxun Yang, Aleksandar Rikalo, Riku Voipio, Daniel P. Berrangé, Huacai Chen, Aurelien Jarno 32-bit host support is deprecated since commit 6d701c9bac1 ("meson: Deprecate 32-bit host support"). Besides, the Debian distribution we are using to cross-build dropped support for MIPS as of Debian 13 [*]: From trixie, the architectures mipsel and mips64el are no longer supported by Debian. Users of these architectures are advised to switch to different hardware. Next commits will remove support for 32-bit MIPS hosts. Stop building the mipsel Docker image. [*] https://www.debian.org/releases/trixie/release-notes/issues.en.html#mips-architectures-removed Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> --- configure | 2 - tests/docker/Makefile.include | 2 +- .../dockerfiles/debian-mipsel-cross.docker | 187 ------------------ tests/lcitool/refresh | 5 - 4 files changed, 1 insertion(+), 195 deletions(-) delete mode 100644 tests/docker/dockerfiles/debian-mipsel-cross.docker diff --git a/configure b/configure index 461b53dd605..6a633ac2b16 100755 --- a/configure +++ b/configure @@ -1360,8 +1360,6 @@ fi : ${cross_prefix_microblaze="microblaze-linux-musl-"} : ${cross_prefix_mips64el="mips64el-linux-gnuabi64-"} : ${cross_prefix_mips64="mips64-linux-gnuabi64-"} -: ${cross_prefix_mipsel="mipsel-linux-gnu-"} -: ${cross_prefix_mips="mips-linux-gnu-"} : ${cross_prefix_ppc="powerpc-linux-gnu-"} : ${cross_prefix_ppc64="powerpc64-linux-gnu-"} : ${cross_prefix_ppc64le="$cross_prefix_ppc64"} diff --git a/tests/docker/Makefile.include b/tests/docker/Makefile.include index 3959d8a028a..ac8ca1fe3a0 100644 --- a/tests/docker/Makefile.include +++ b/tests/docker/Makefile.include @@ -82,7 +82,7 @@ endif # For non-x86 hosts not all cross-compilers have been packaged ifneq ($(HOST_ARCH),x86_64) -DOCKER_PARTIAL_IMAGES += debian-mipsel-cross debian-mips64el-cross +DOCKER_PARTIAL_IMAGES += debian-mips64el-cross DOCKER_PARTIAL_IMAGES += debian-ppc64el-cross DOCKER_PARTIAL_IMAGES += debian-s390x-cross DOCKER_PARTIAL_IMAGES += fedora diff --git a/tests/docker/dockerfiles/debian-mipsel-cross.docker b/tests/docker/dockerfiles/debian-mipsel-cross.docker deleted file mode 100644 index 5f4e3fa9636..00000000000 --- a/tests/docker/dockerfiles/debian-mipsel-cross.docker +++ /dev/null @@ -1,187 +0,0 @@ -# THIS FILE WAS AUTO-GENERATED -# -# $ lcitool dockerfile --layers all --cross-arch mipsel debian-12 qemu -# -# https://gitlab.com/libvirt/libvirt-ci - -FROM docker.io/library/debian:12-slim - -RUN export DEBIAN_FRONTEND=noninteractive && \ - apt-get update && \ - apt-get install -y eatmydata && \ - eatmydata apt-get dist-upgrade -y && \ - eatmydata apt-get install --no-install-recommends -y \ - bash \ - bc \ - bindgen \ - bison \ - bsdextrautils \ - bzip2 \ - ca-certificates \ - ccache \ - dbus \ - debianutils \ - diffutils \ - exuberant-ctags \ - findutils \ - flex \ - gcc \ - gcovr \ - gettext \ - git \ - hostname \ - libclang-rt-dev \ - libglib2.0-dev \ - llvm \ - locales \ - make \ - mtools \ - ncat \ - ninja-build \ - openssh-client \ - pkgconf \ - python3 \ - python3-numpy \ - python3-opencv \ - python3-pillow \ - python3-pip \ - python3-setuptools \ - python3-sphinx \ - python3-sphinx-rtd-theme \ - python3-venv \ - python3-wheel \ - python3-yaml \ - rpm2cpio \ - rustc-web \ - sed \ - socat \ - sparse \ - swtpm \ - tar \ - tesseract-ocr \ - tesseract-ocr-eng \ - vulkan-tools \ - xorriso \ - zstd && \ - eatmydata apt-get autoremove -y && \ - eatmydata apt-get autoclean -y && \ - sed -Ei 's,^# (en_US\.UTF-8 .*)$,\1,' /etc/locale.gen && \ - dpkg-reconfigure locales && \ - rm -f /usr/lib*/python3*/EXTERNALLY-MANAGED - -RUN /usr/bin/pip3 install meson==1.8.1 - -ENV CCACHE_WRAPPERSDIR "/usr/libexec/ccache-wrappers" -ENV LANG "en_US.UTF-8" -ENV MAKE "/usr/bin/make" -ENV NINJA "/usr/bin/ninja" -ENV PYTHON "/usr/bin/python3" - -RUN export DEBIAN_FRONTEND=noninteractive && \ - dpkg --add-architecture mipsel && \ - eatmydata apt-get update && \ - eatmydata apt-get dist-upgrade -y && \ - eatmydata apt-get install --no-install-recommends -y dpkg-dev && \ - eatmydata apt-get install --no-install-recommends -y \ - gcc-mipsel-linux-gnu \ - libaio-dev:mipsel \ - libasound2-dev:mipsel \ - libattr1-dev:mipsel \ - libbpf-dev:mipsel \ - libbrlapi-dev:mipsel \ - libbz2-dev:mipsel \ - libc6-dev:mipsel \ - libcacard-dev:mipsel \ - libcap-ng-dev:mipsel \ - libcapstone-dev:mipsel \ - libcbor-dev:mipsel \ - libcmocka-dev:mipsel \ - libcurl4-gnutls-dev:mipsel \ - libdaxctl-dev:mipsel \ - libdrm-dev:mipsel \ - libepoxy-dev:mipsel \ - libfdt-dev:mipsel \ - libffi-dev:mipsel \ - libfuse3-dev:mipsel \ - libgbm-dev:mipsel \ - libgcrypt20-dev:mipsel \ - libglib2.0-dev:mipsel \ - libglusterfs-dev:mipsel \ - libgnutls28-dev:mipsel \ - libgtk-3-dev:mipsel \ - libgtk-vnc-2.0-dev:mipsel \ - libibverbs-dev:mipsel \ - libiscsi-dev:mipsel \ - libjemalloc-dev:mipsel \ - libjpeg62-turbo-dev:mipsel \ - libjson-c-dev:mipsel \ - liblttng-ust-dev:mipsel \ - liblzo2-dev:mipsel \ - libncursesw5-dev:mipsel \ - libnfs-dev:mipsel \ - libnuma-dev:mipsel \ - libpam0g-dev:mipsel \ - libpcre2-dev:mipsel \ - libpipewire-0.3-dev:mipsel \ - libpixman-1-dev:mipsel \ - libpng-dev:mipsel \ - libpulse-dev:mipsel \ - librbd-dev:mipsel \ - librdmacm-dev:mipsel \ - libsasl2-dev:mipsel \ - libsdl2-dev:mipsel \ - libsdl2-image-dev:mipsel \ - libseccomp-dev:mipsel \ - libselinux1-dev:mipsel \ - libslirp-dev:mipsel \ - libsnappy-dev:mipsel \ - libsndio-dev:mipsel \ - libspice-protocol-dev:mipsel \ - libspice-server-dev:mipsel \ - libssh-dev:mipsel \ - libstd-rust-dev:mipsel \ - libsystemd-dev:mipsel \ - libtasn1-6-dev:mipsel \ - libudev-dev:mipsel \ - liburing-dev:mipsel \ - libusb-1.0-0-dev:mipsel \ - libusbredirhost-dev:mipsel \ - libvdeplug-dev:mipsel \ - libvirglrenderer-dev:mipsel \ - libvte-2.91-dev:mipsel \ - libxdp-dev:mipsel \ - libzstd-dev:mipsel \ - nettle-dev:mipsel \ - systemtap-sdt-dev:mipsel \ - zlib1g-dev:mipsel && \ - eatmydata apt-get autoremove -y && \ - eatmydata apt-get autoclean -y && \ - mkdir -p /usr/local/share/meson/cross && \ - printf "[binaries]\n\ -c = '/usr/bin/mipsel-linux-gnu-gcc'\n\ -ar = '/usr/bin/mipsel-linux-gnu-gcc-ar'\n\ -strip = '/usr/bin/mipsel-linux-gnu-strip'\n\ -pkgconfig = '/usr/bin/mipsel-linux-gnu-pkg-config'\n\ -\n\ -[host_machine]\n\ -system = 'linux'\n\ -cpu_family = 'mips'\n\ -cpu = 'mipsel'\n\ -endian = 'little'\n" > /usr/local/share/meson/cross/mipsel-linux-gnu && \ - dpkg-query --showformat '${Package}_${Version}_${Architecture}\n' --show > /packages.txt && \ - mkdir -p /usr/libexec/ccache-wrappers && \ - ln -s /usr/bin/ccache /usr/libexec/ccache-wrappers/mipsel-linux-gnu-cc && \ - ln -s /usr/bin/ccache /usr/libexec/ccache-wrappers/mipsel-linux-gnu-gcc - -ENV ABI "mipsel-linux-gnu" -ENV MESON_OPTS "--cross-file=mipsel-linux-gnu" -ENV RUST_TARGET "mipsel-unknown-linux-gnu" -ENV QEMU_CONFIGURE_OPTS --cross-prefix=mipsel-linux-gnu- -ENV DEF_TARGET_LIST mipsel-softmmu,mipsel-linux-user -# As a final step configure the user (if env is defined) -ARG USER -ARG UID -RUN if [ "${USER}" ]; then \ - id ${USER} 2>/dev/null || useradd -u ${UID} -U ${USER}; fi - -ENV ENABLE_RUST 1 diff --git a/tests/lcitool/refresh b/tests/lcitool/refresh index 056cfb6e9d7..39bfc7e1113 100755 --- a/tests/lcitool/refresh +++ b/tests/lcitool/refresh @@ -225,11 +225,6 @@ try: trailer=cross_build("mips64el-linux-gnuabi64-", "mips64el-softmmu,mips64el-linux-user")) - generate_dockerfile("debian-mipsel-cross", "debian-12", - cross="mipsel", - trailer=cross_build("mipsel-linux-gnu-", - "mipsel-softmmu,mipsel-linux-user")) - generate_dockerfile("debian-ppc64el-cross", "debian-13", cross="ppc64le", trailer=cross_build("powerpc64le-linux-gnu-", -- 2.51.0 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 4/7] tcg/mips: Remove support for O32 and N32 ABIs 2025-10-09 19:52 [PATCH v2 0/7] tcg/mips: Remove support for 32-bit hosts Philippe Mathieu-Daudé ` (2 preceding siblings ...) 2025-10-09 19:52 ` [PATCH v2 3/7] docker: Stop building 32-bit MIPS images Philippe Mathieu-Daudé @ 2025-10-09 19:52 ` Philippe Mathieu-Daudé 2025-10-10 6:45 ` Thomas Huth 2025-10-09 19:52 ` [PATCH v2 5/7] tcg/mips: Remove support for 32-bit hosts Philippe Mathieu-Daudé ` (2 subsequent siblings) 6 siblings, 1 reply; 14+ messages in thread From: Philippe Mathieu-Daudé @ 2025-10-09 19:52 UTC (permalink / raw) To: qemu-devel Cc: Alex Bennée, Thomas Huth, Paolo Bonzini, Richard Henderson, Marc-André Lureau, Philippe Mathieu-Daudé, devel, Jiaxun Yang, Aleksandar Rikalo, Riku Voipio, Daniel P. Berrangé, Huacai Chen, Aurelien Jarno See previous commit for rationale. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- tcg/mips/tcg-target-reg-bits.h | 9 ++---- tcg/mips/tcg-target.c.inc | 15 ++-------- common-user/host/mips/safe-syscall.inc.S | 35 ------------------------ 3 files changed, 6 insertions(+), 53 deletions(-) diff --git a/tcg/mips/tcg-target-reg-bits.h b/tcg/mips/tcg-target-reg-bits.h index a957d2312f3..ee346a3f256 100644 --- a/tcg/mips/tcg-target-reg-bits.h +++ b/tcg/mips/tcg-target-reg-bits.h @@ -7,13 +7,10 @@ #ifndef TCG_TARGET_REG_BITS_H #define TCG_TARGET_REG_BITS_H -#if defined(_ABIO32) && _MIPS_SIM == _ABIO32 -# define TCG_TARGET_REG_BITS 32 -#elif (defined(_ABIN32) && _MIPS_SIM == _ABIN32) \ - || (defined(_ABI64) && _MIPS_SIM == _ABI64) -# define TCG_TARGET_REG_BITS 64 -#else +#if !defined(_MIPS_SIM) || _MIPS_SIM != _ABI64 # error "Unknown ABI" #endif +#define TCG_TARGET_REG_BITS 64 + #endif diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 045565f4ca8..77af0d8658a 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -26,15 +26,9 @@ /* used for function call generation */ #define TCG_TARGET_STACK_ALIGN 16 -#if defined(_ABIO32) && _MIPS_SIM == _ABIO32 -# define TCG_TARGET_CALL_STACK_OFFSET 16 -# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN -# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF -#else -# define TCG_TARGET_CALL_STACK_OFFSET 0 -# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL -# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL -#endif +#define TCG_TARGET_CALL_STACK_OFFSET 0 +#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN @@ -135,13 +129,10 @@ static const TCGReg tcg_target_call_iarg_regs[] = { TCG_REG_A1, TCG_REG_A2, TCG_REG_A3, -#if (defined(_ABIN32) && _MIPS_SIM == _ABIN32) \ - || (defined(_ABI64) && _MIPS_SIM == _ABI64) TCG_REG_T0, TCG_REG_T1, TCG_REG_T2, TCG_REG_T3, -#endif }; static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) diff --git a/common-user/host/mips/safe-syscall.inc.S b/common-user/host/mips/safe-syscall.inc.S index 8857d708dae..3b196cc634c 100644 --- a/common-user/host/mips/safe-syscall.inc.S +++ b/common-user/host/mips/safe-syscall.inc.S @@ -30,15 +30,9 @@ * arguments being syscall arguments (also 'long'). */ -#if defined(_ABIO32) && _MIPS_SIM == _ABIO32 -/* 8 * 4 = 32 for outgoing parameters; 1 * 4 for s0 save; 1 * 4 for align. */ -#define FRAME 40 -#define OFS_S0 32 -#else /* 1 * 8 for s0 save; 1 * 8 for align. */ #define FRAME 16 #define OFS_S0 0 -#endif NESTED(safe_syscall_base, FRAME, ra) @@ -47,34 +41,6 @@ NESTED(safe_syscall_base, FRAME, ra) .cfi_adjust_cfa_offset FRAME REG_S s0, OFS_S0(sp) .cfi_rel_offset s0, OFS_S0 -#if defined(_ABIO32) && _MIPS_SIM == _ABIO32 - /* - * The syscall calling convention is nearly the same as C: - * we enter with a0 == &signal_pending - * a1 == syscall number - * a2, a3, stack == syscall arguments - * and return the result in a0 - * and the syscall instruction needs - * v0 == syscall number - * a0 ... a3, stack == syscall arguments - * and returns the result in v0 - * Shuffle everything around appropriately. - */ - move s0, a0 /* signal_pending pointer */ - move v0, a1 /* syscall number */ - move a0, a2 /* syscall arguments */ - move a1, a3 - lw a2, FRAME+16(sp) - lw a3, FRAME+20(sp) - lw t4, FRAME+24(sp) - lw t5, FRAME+28(sp) - lw t6, FRAME+32(sp) - lw t7, FRAME+40(sp) - sw t4, 16(sp) - sw t5, 20(sp) - sw t6, 24(sp) - sw t7, 28(sp) -#else /* * The syscall calling convention is nearly the same as C: * we enter with a0 == &signal_pending @@ -95,7 +61,6 @@ NESTED(safe_syscall_base, FRAME, ra) move a3, a5 move a4, a6 move a5, a7 -#endif /* * This next sequence of code works in conjunction with the -- 2.51.0 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v2 4/7] tcg/mips: Remove support for O32 and N32 ABIs 2025-10-09 19:52 ` [PATCH v2 4/7] tcg/mips: Remove support for O32 and N32 ABIs Philippe Mathieu-Daudé @ 2025-10-10 6:45 ` Thomas Huth 0 siblings, 0 replies; 14+ messages in thread From: Thomas Huth @ 2025-10-10 6:45 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel Cc: Alex Bennée, Paolo Bonzini, Richard Henderson, Marc-André Lureau, devel, Jiaxun Yang, Aleksandar Rikalo, Riku Voipio, Daniel P. Berrangé, Huacai Chen, Aurelien Jarno On 09/10/2025 21.52, Philippe Mathieu-Daudé wrote: > See previous commit for rationale. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > tcg/mips/tcg-target-reg-bits.h | 9 ++---- > tcg/mips/tcg-target.c.inc | 15 ++-------- > common-user/host/mips/safe-syscall.inc.S | 35 ------------------------ > 3 files changed, 6 insertions(+), 53 deletions(-) Reviewed-by: Thomas Huth <thuth@redhat.com> ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 5/7] tcg/mips: Remove support for 32-bit hosts 2025-10-09 19:52 [PATCH v2 0/7] tcg/mips: Remove support for 32-bit hosts Philippe Mathieu-Daudé ` (3 preceding siblings ...) 2025-10-09 19:52 ` [PATCH v2 4/7] tcg/mips: Remove support for O32 and N32 ABIs Philippe Mathieu-Daudé @ 2025-10-09 19:52 ` Philippe Mathieu-Daudé 2025-10-10 6:51 ` Thomas Huth 2025-10-09 19:52 ` [PATCH v2 6/7] kvm/mips: " Philippe Mathieu-Daudé 2025-10-09 19:52 ` [PATCH v2 7/7] buildsys: Remove support for 32-bit MIPS hosts Philippe Mathieu-Daudé 6 siblings, 1 reply; 14+ messages in thread From: Philippe Mathieu-Daudé @ 2025-10-09 19:52 UTC (permalink / raw) To: qemu-devel Cc: Alex Bennée, Thomas Huth, Paolo Bonzini, Richard Henderson, Marc-André Lureau, Philippe Mathieu-Daudé, devel, Jiaxun Yang, Aleksandar Rikalo, Riku Voipio, Daniel P. Berrangé, Huacai Chen, Aurelien Jarno 32-bit host support is deprecated since commit 6d701c9bac1 ("meson: Deprecate 32-bit host support"), released as v10.0. The next release being v10.2, we can remove the TCG backend for 32-bit MIPS hosts. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/mips/tcg-target-has.h | 2 - tcg/mips/tcg-target.c.inc | 277 ++++++-------------------------------- 2 files changed, 38 insertions(+), 241 deletions(-) diff --git a/tcg/mips/tcg-target-has.h b/tcg/mips/tcg-target-has.h index b9eb3385288..88f0145efba 100644 --- a/tcg/mips/tcg-target-has.h +++ b/tcg/mips/tcg-target-has.h @@ -39,11 +39,9 @@ extern bool use_mips32r2_instructions; #endif /* optional instructions */ -#if TCG_TARGET_REG_BITS == 64 #define TCG_TARGET_HAS_extr_i64_i32 1 #define TCG_TARGET_HAS_ext32s_i64 1 #define TCG_TARGET_HAS_ext32u_i64 1 -#endif /* optional instructions detected at runtime */ #define TCG_TARGET_HAS_qemu_ldst_i128 0 diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 77af0d8658a..c52f749b43b 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -32,15 +32,6 @@ #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN -#if TCG_TARGET_REG_BITS == 32 -# define LO_OFF (HOST_BIG_ENDIAN * 4) -# define HI_OFF (4 - LO_OFF) -#else -/* Assert at compile-time that these values are never used for 64-bit. */ -# define LO_OFF ({ qemu_build_not_reached(); 0; }) -# define HI_OFF ({ qemu_build_not_reached(); 0; }) -#endif - #ifdef CONFIG_DEBUG_TCG static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { "zero", @@ -84,11 +75,7 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { #define TCG_TMP3 TCG_REG_T7 #define TCG_GUEST_BASE_REG TCG_REG_S7 -#if TCG_TARGET_REG_BITS == 64 #define TCG_REG_TB TCG_REG_S6 -#else -#define TCG_REG_TB ({ qemu_build_not_reached(); TCG_REG_ZERO; }) -#endif /* check if we really need so many registers :P */ static const int tcg_target_reg_alloc_order[] = { @@ -559,7 +546,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long tmp; int sh, lo; - if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { + if (type == TCG_TYPE_I32) { arg = (int32_t)arg; } @@ -567,7 +554,6 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, if (tcg_out_movi_two(s, ret, arg)) { return; } - assert(TCG_TARGET_REG_BITS == 64); /* Load addresses within 2GB of TB with 1 or 3 insns. */ tmp = tcg_tbrel_diff(s, (void *)arg); @@ -630,7 +616,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg) { - TCGReg tbreg = TCG_TARGET_REG_BITS == 64 ? TCG_REG_TB : 0; + TCGReg tbreg = TCG_REG_TB; tcg_out_movi_int(s, type, ret, arg, tbreg); } @@ -658,7 +644,6 @@ static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rs) static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rs) { - tcg_debug_assert(TCG_TARGET_REG_BITS == 64); tcg_out_opc_sa(s, OPC_SLL, rd, rs, 0); } @@ -701,7 +686,6 @@ static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub) static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) { - tcg_debug_assert(TCG_TARGET_REG_BITS == 64); if (use_mips32r2_instructions) { tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0); } else { @@ -728,7 +712,7 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, intptr_t arg2) { MIPSInsn opc = OPC_LD; - if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { + if (type == TCG_TYPE_I32) { opc = OPC_LW; } tcg_out_ldst(s, opc, arg, arg1, arg2); @@ -738,7 +722,7 @@ static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, intptr_t arg2) { MIPSInsn opc = OPC_SD; - if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { + if (type == TCG_TYPE_I32) { opc = OPC_SW; } tcg_out_ldst(s, opc, arg, arg1, arg2); @@ -918,72 +902,6 @@ void tcg_out_br(TCGContext *s, TCGLabel *l) tgen_brcond(s, TCG_TYPE_I32, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO, l); } -static int tcg_out_setcond2_int(TCGContext *s, TCGCond cond, TCGReg ret, - TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) -{ - int flags = 0; - - switch (cond) { - case TCG_COND_EQ: - flags |= SETCOND_INV; - /* fall through */ - case TCG_COND_NE: - flags |= SETCOND_NEZ; - tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, al, bl); - tcg_out_opc_reg(s, OPC_XOR, TCG_TMP1, ah, bh); - tcg_out_opc_reg(s, OPC_OR, ret, TCG_TMP0, TCG_TMP1); - break; - - default: - tgen_setcond(s, TCG_TYPE_I32, TCG_COND_EQ, TCG_TMP0, ah, bh); - tgen_setcond(s, TCG_TYPE_I32, tcg_unsigned_cond(cond), - TCG_TMP1, al, bl); - tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP0); - tgen_setcond(s, TCG_TYPE_I32, tcg_high_cond(cond), TCG_TMP0, ah, bh); - tcg_out_opc_reg(s, OPC_OR, ret, TCG_TMP0, TCG_TMP1); - break; - } - return ret | flags; -} - -static void tgen_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, - TCGReg al, TCGReg ah, - TCGArg bl, bool const_bl, - TCGArg bh, bool const_bh) -{ - int tmpflags = tcg_out_setcond2_int(s, cond, ret, al, ah, bl, bh); - tcg_out_setcond_end(s, ret, tmpflags); -} - -#if TCG_TARGET_REG_BITS != 32 -__attribute__((unused)) -#endif -static const TCGOutOpSetcond2 outop_setcond2 = { - .base.static_constraint = C_O1_I4(r, r, r, rz, rz), - .out = tgen_setcond2, -}; - -static void tgen_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, - TCGArg bl, bool const_bl, - TCGArg bh, bool const_bh, TCGLabel *l) -{ - int tmpflags = tcg_out_setcond2_int(s, cond, TCG_TMP0, al, ah, bl, bh); - TCGReg tmp = tmpflags & ~SETCOND_FLAGS; - MIPSInsn b_opc = tmpflags & SETCOND_INV ? OPC_BEQ : OPC_BNE; - - tcg_out_reloc(s, s->code_ptr, R_MIPS_PC16, l, 0); - tcg_out_opc_br(s, b_opc, tmp, TCG_REG_ZERO); - tcg_out_nop(s); -} - -#if TCG_TARGET_REG_BITS != 32 -__attribute__((unused)) -#endif -static const TCGOutOpBrcond2 outop_brcond2 = { - .base.static_constraint = C_O0_I4(r, r, rz, rz), - .out = tgen_brcond2, -}; - static void tgen_movcond(TCGContext *s, TCGType type, TCGCond cond, TCGReg ret, TCGReg c1, TCGArg c2, bool const_c2, TCGArg v1, bool const_v1, TCGArg v2, bool const_v2) @@ -1189,7 +1107,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); /* Extract the TLB index from the address into TMP3. */ - if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) { + if (addr_type == TCG_TYPE_I32) { tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, addr, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); } else { @@ -1201,7 +1119,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); /* Load the tlb comparator. */ - if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { + if (addr_type == TCG_TYPE_I32) { tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, cmp_off + HOST_BIG_ENDIAN * 4); } else { @@ -1218,8 +1136,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, */ tcg_out_movi(s, addr_type, TCG_TMP1, TARGET_PAGE_MASK | a_mask); if (a_mask < s_mask) { - tcg_out_opc_imm(s, (TCG_TARGET_REG_BITS == 32 - || addr_type == TCG_TYPE_I32 + tcg_out_opc_imm(s, (addr_type == TCG_TYPE_I32 ? OPC_ADDIU : OPC_DADDIU), TCG_TMP2, addr, s_mask - a_mask); tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2); @@ -1228,7 +1145,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, } /* Zero extend a 32-bit guest address for a 64-bit host. */ - if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { + if (addr_type == TCG_TYPE_I32) { tcg_out_ext32u(s, TCG_TMP2, addr); addr = TCG_TMP2; } @@ -1261,7 +1178,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, } base = addr; - if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { + if (addr_type == TCG_TYPE_I32) { tcg_out_ext32u(s, TCG_REG_A0, base); base = TCG_REG_A0; } @@ -1297,7 +1214,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, tcg_out_opc_imm(s, OPC_LH, lo, base, 0); break; case MO_UL: - if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64) { + if (type == TCG_TYPE_I64) { tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); break; } @@ -1307,15 +1224,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, break; case MO_UQ: /* Prefer to load from offset 0 first, but allow for overlap. */ - if (TCG_TARGET_REG_BITS == 64) { - tcg_out_opc_imm(s, OPC_LD, lo, base, 0); - } else if (HOST_BIG_ENDIAN ? hi != base : lo == base) { - tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); - tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); - } else { - tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); - tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); - } + tcg_out_opc_imm(s, OPC_LD, lo, base, 0); break; default: g_assert_not_reached(); @@ -1357,21 +1266,14 @@ static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi, case MO_32: tcg_out_opc_imm(s, lw1, lo, base, 0); tcg_out_opc_imm(s, lw2, lo, base, 3); - if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64 && !sgn) { + if (type == TCG_TYPE_I64 && !sgn) { tcg_out_ext32u(s, lo, lo); } break; case MO_64: - if (TCG_TARGET_REG_BITS == 64) { - tcg_out_opc_imm(s, ld1, lo, base, 0); - tcg_out_opc_imm(s, ld2, lo, base, 7); - } else { - tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0); - tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3); - tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0); - tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3); - } + tcg_out_opc_imm(s, ld1, lo, base, 0); + tcg_out_opc_imm(s, ld2, lo, base, 7); break; default: @@ -1407,36 +1309,8 @@ static const TCGOutOpQemuLdSt outop_qemu_ld = { .out = tgen_qemu_ld, }; -static void tgen_qemu_ld2(TCGContext *s, TCGType type, TCGReg datalo, - TCGReg datahi, TCGReg addr, MemOpIdx oi) -{ - MemOp opc = get_memop(oi); - TCGLabelQemuLdst *ldst; - HostAddress h; - - tcg_debug_assert(TCG_TARGET_REG_BITS == 32); - ldst = prepare_host_addr(s, &h, addr, oi, true); - - if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) { - tcg_out_qemu_ld_direct(s, datalo, datahi, h.base, opc, type); - } else { - tcg_out_qemu_ld_unalign(s, datalo, datahi, h.base, opc, type); - } - - if (ldst) { - ldst->type = type; - ldst->datalo_reg = datalo; - ldst->datahi_reg = datahi; - ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); - } -} - static const TCGOutOpQemuLdSt2 outop_qemu_ld2 = { - /* Ensure that the mips32 code is compiled but discarded for mips64. */ - .base.static_constraint = - TCG_TARGET_REG_BITS == 32 ? C_O2_I1(r, r, r) : C_NotImplemented, - .out = - TCG_TARGET_REG_BITS == 32 ? tgen_qemu_ld2 : NULL, + .base.static_constraint = C_NotImplemented, }; static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, @@ -1453,12 +1327,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, tcg_out_opc_imm(s, OPC_SW, lo, base, 0); break; case MO_64: - if (TCG_TARGET_REG_BITS == 64) { - tcg_out_opc_imm(s, OPC_SD, lo, base, 0); - } else { - tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? hi : lo, base, 0); - tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? lo : hi, base, 4); - } + tcg_out_opc_imm(s, OPC_SD, lo, base, 0); break; default: g_assert_not_reached(); @@ -1486,15 +1355,8 @@ static void tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi, break; case MO_64: - if (TCG_TARGET_REG_BITS == 64) { - tcg_out_opc_imm(s, sd1, lo, base, 0); - tcg_out_opc_imm(s, sd2, lo, base, 7); - } else { - tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0); - tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3); - tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0); - tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3); - } + tcg_out_opc_imm(s, sd1, lo, base, 0); + tcg_out_opc_imm(s, sd2, lo, base, 7); break; default: @@ -1530,36 +1392,8 @@ static const TCGOutOpQemuLdSt outop_qemu_st = { .out = tgen_qemu_st, }; -static void tgen_qemu_st2(TCGContext *s, TCGType type, TCGReg datalo, - TCGReg datahi, TCGReg addr, MemOpIdx oi) -{ - MemOp opc = get_memop(oi); - TCGLabelQemuLdst *ldst; - HostAddress h; - - tcg_debug_assert(TCG_TARGET_REG_BITS == 32); - ldst = prepare_host_addr(s, &h, addr, oi, false); - - if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) { - tcg_out_qemu_st_direct(s, datalo, datahi, h.base, opc); - } else { - tcg_out_qemu_st_unalign(s, datalo, datahi, h.base, opc); - } - - if (ldst) { - ldst->type = type; - ldst->datalo_reg = datalo; - ldst->datahi_reg = datahi; - ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); - } -} - static const TCGOutOpQemuLdSt2 outop_qemu_st2 = { - /* Ensure that the mips32 code is compiled but discarded for mips64. */ - .base.static_constraint = - TCG_TARGET_REG_BITS == 32 ? C_O0_I3(rz, rz, r) : C_NotImplemented, - .out = - TCG_TARGET_REG_BITS == 32 ? tgen_qemu_st2 : NULL, + .base.static_constraint = C_NotImplemented, }; static void tcg_out_mb(TCGContext *s, unsigned a0) @@ -1584,22 +1418,14 @@ static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) int16_t lo = 0; if (a0) { - intptr_t ofs; - if (TCG_TARGET_REG_BITS == 64) { - ofs = tcg_tbrel_diff(s, (void *)a0); - lo = ofs; - if (ofs == lo) { - base = TCG_REG_TB; - } else { - base = TCG_REG_V0; - tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo); - tcg_out_opc_reg(s, ALIAS_PADD, base, base, TCG_REG_TB); - } + intptr_t ofs = tcg_tbrel_diff(s, (void *)a0); + lo = ofs; + if (ofs == lo) { + base = TCG_REG_TB; } else { - ofs = a0; - lo = ofs; base = TCG_REG_V0; tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo); + tcg_out_opc_reg(s, ALIAS_PADD, base, base, TCG_REG_TB); } } if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) { @@ -1616,35 +1442,24 @@ static void tcg_out_goto_tb(TCGContext *s, int which) TCGReg base, dest; /* indirect jump method */ - if (TCG_TARGET_REG_BITS == 64) { - dest = TCG_REG_TB; - base = TCG_REG_TB; - ofs = tcg_tbrel_diff(s, (void *)ofs); - } else { - dest = TCG_TMP0; - base = TCG_REG_ZERO; - } + dest = TCG_REG_TB; + base = TCG_REG_TB; + ofs = tcg_tbrel_diff(s, (void *)ofs); tcg_out_ld(s, TCG_TYPE_PTR, dest, base, ofs); tcg_out_opc_reg(s, OPC_JR, 0, dest, 0); /* delay slot */ tcg_out_nop(s); set_jmp_reset_offset(s, which); - if (TCG_TARGET_REG_BITS == 64) { - /* For the unlinked case, need to reset TCG_REG_TB. */ - tcg_out_ldst(s, ALIAS_PADDI, TCG_REG_TB, TCG_REG_TB, - -tcg_current_code_size(s)); - } + /* For the unlinked case, need to reset TCG_REG_TB. */ + tcg_out_ldst(s, ALIAS_PADDI, TCG_REG_TB, TCG_REG_TB, + -tcg_current_code_size(s)); } static void tcg_out_goto_ptr(TCGContext *s, TCGReg a0) { tcg_out_opc_reg(s, OPC_JR, 0, a0, 0); - if (TCG_TARGET_REG_BITS == 64) { - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); - } else { - tcg_out_nop(s); - } + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); } void tb_target_set_jmp_target(const TranslationBlock *tb, int n, @@ -1839,7 +1654,6 @@ static const TCGOutOpBinary outop_eqv = { .base.static_constraint = C_NotImplemented, }; -#if TCG_TARGET_REG_BITS == 64 static void tgen_extrh_i64_i32(TCGContext *s, TCGType t, TCGReg a0, TCGReg a1) { tcg_out_dsra(s, a0, a1, 32); @@ -1849,7 +1663,6 @@ static const TCGOutOpUnary outop_extrh_i64_i32 = { .base.static_constraint = C_O1_I1(r, r), .out_rr = tgen_extrh_i64_i32, }; -#endif static void tgen_mul(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, TCGReg a2) @@ -2238,7 +2051,6 @@ static const TCGOutOpBswap outop_bswap32 = { .out_rr = tgen_bswap32, }; -#if TCG_TARGET_REG_BITS == 64 static void tgen_bswap64(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) { if (use_mips32r2_instructions) { @@ -2256,7 +2068,6 @@ static const TCGOutOpUnary outop_bswap64 = { .base.static_constraint = C_O1_I1(r, r), .out_rr = tgen_bswap64, }; -#endif /* TCG_TARGET_REG_BITS == 64 */ static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) { @@ -2384,7 +2195,6 @@ static const TCGOutOpLoad outop_ld16s = { .out = tgen_ld16s, }; -#if TCG_TARGET_REG_BITS == 64 static void tgen_ld32u(TCGContext *s, TCGType type, TCGReg dest, TCGReg base, ptrdiff_t offset) { @@ -2406,7 +2216,6 @@ static const TCGOutOpLoad outop_ld32s = { .base.static_constraint = C_O1_I1(r, r), .out = tgen_ld32s, }; -#endif static void tgen_st8_r(TCGContext *s, TCGType type, TCGReg data, TCGReg base, ptrdiff_t offset) @@ -2549,7 +2358,7 @@ static tcg_insn_unit *align_code_ptr(TCGContext *s) } /* Stack frame parameters. */ -#define REG_SIZE (TCG_TARGET_REG_BITS / 8) +#define REG_SIZE 8 #define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) #define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) @@ -2581,17 +2390,15 @@ static void tcg_target_qemu_prologue(TCGContext *s) * with the address of the prologue, so we can use that instead * of TCG_REG_TB. */ -#if TCG_TARGET_REG_BITS == 64 && !defined(__mips_abicalls) +#if !defined(__mips_abicalls) # error "Unknown mips abi" #endif tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, - TCG_TARGET_REG_BITS == 64 ? TCG_REG_T9 : 0); + TCG_REG_T9); tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); } - if (TCG_TARGET_REG_BITS == 64) { - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]); - } + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]); /* Call generated code */ tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0); @@ -2647,10 +2454,6 @@ static void tcg_target_qemu_prologue(TCGContext *s) /* t3 = dcba -- delay slot */ tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); - if (TCG_TARGET_REG_BITS == 32) { - return; - } - /* * bswap32u -- unsigned 32-bit swap. a0 = ....abcd. */ @@ -2745,9 +2548,7 @@ static void tcg_target_init(TCGContext *s) { tcg_target_detect_isa(); tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; - if (TCG_TARGET_REG_BITS == 64) { - tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; - } + tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; tcg_target_call_clobber_regs = 0; tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); @@ -2778,9 +2579,7 @@ static void tcg_target_init(TCGContext *s) tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */ - if (TCG_TARGET_REG_BITS == 64) { - tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tc->tc_ptr */ - } + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tc->tc_ptr */ } typedef struct { @@ -2798,7 +2597,7 @@ static const DebugFrame debug_frame = { .h.cie.id = -1, .h.cie.version = 1, .h.cie.code_align = 1, - .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ + .h.cie.data_align = -REG_SIZE & 0x7f, /* sleb128 */ .h.cie.return_column = TCG_REG_RA, /* Total FDE size does not include the "len" member. */ -- 2.51.0 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v2 5/7] tcg/mips: Remove support for 32-bit hosts 2025-10-09 19:52 ` [PATCH v2 5/7] tcg/mips: Remove support for 32-bit hosts Philippe Mathieu-Daudé @ 2025-10-10 6:51 ` Thomas Huth 0 siblings, 0 replies; 14+ messages in thread From: Thomas Huth @ 2025-10-10 6:51 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel Cc: Alex Bennée, Paolo Bonzini, Richard Henderson, Marc-André Lureau, devel, Jiaxun Yang, Aleksandar Rikalo, Riku Voipio, Daniel P. Berrangé, Huacai Chen, Aurelien Jarno On 09/10/2025 21.52, Philippe Mathieu-Daudé wrote: > 32-bit host support is deprecated since commit 6d701c9bac1 > ("meson: Deprecate 32-bit host support"), released as v10.0. > The next release being v10.2, we can remove the TCG backend > for 32-bit MIPS hosts. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > --- > tcg/mips/tcg-target-has.h | 2 - > tcg/mips/tcg-target.c.inc | 277 ++++++-------------------------------- > 2 files changed, 38 insertions(+), 241 deletions(-) Reviewed-by: Thomas Huth <thuth@redhat.com> ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 6/7] kvm/mips: Remove support for 32-bit hosts 2025-10-09 19:52 [PATCH v2 0/7] tcg/mips: Remove support for 32-bit hosts Philippe Mathieu-Daudé ` (4 preceding siblings ...) 2025-10-09 19:52 ` [PATCH v2 5/7] tcg/mips: Remove support for 32-bit hosts Philippe Mathieu-Daudé @ 2025-10-09 19:52 ` Philippe Mathieu-Daudé 2025-10-10 6:52 ` Thomas Huth 2025-10-09 19:52 ` [PATCH v2 7/7] buildsys: Remove support for 32-bit MIPS hosts Philippe Mathieu-Daudé 6 siblings, 1 reply; 14+ messages in thread From: Philippe Mathieu-Daudé @ 2025-10-09 19:52 UTC (permalink / raw) To: qemu-devel Cc: Alex Bennée, Thomas Huth, Paolo Bonzini, Richard Henderson, Marc-André Lureau, Philippe Mathieu-Daudé, devel, Jiaxun Yang, Aleksandar Rikalo, Riku Voipio, Daniel P. Berrangé, Huacai Chen, Aurelien Jarno See previous commit for rationale. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- meson.build | 2 -- 1 file changed, 2 deletions(-) diff --git a/meson.build b/meson.build index afaefa01722..c5710a6a47c 100644 --- a/meson.build +++ b/meson.build @@ -295,8 +295,6 @@ elif cpu == 'ppc' kvm_targets = ['ppc-softmmu'] elif cpu == 'ppc64' kvm_targets = ['ppc-softmmu', 'ppc64-softmmu'] -elif cpu == 'mips' - kvm_targets = ['mips-softmmu', 'mipsel-softmmu'] elif cpu == 'mips64' kvm_targets = ['mips-softmmu', 'mipsel-softmmu', 'mips64-softmmu', 'mips64el-softmmu'] elif cpu == 'riscv32' -- 2.51.0 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v2 6/7] kvm/mips: Remove support for 32-bit hosts 2025-10-09 19:52 ` [PATCH v2 6/7] kvm/mips: " Philippe Mathieu-Daudé @ 2025-10-10 6:52 ` Thomas Huth 0 siblings, 0 replies; 14+ messages in thread From: Thomas Huth @ 2025-10-10 6:52 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel Cc: Alex Bennée, Paolo Bonzini, Richard Henderson, Marc-André Lureau, devel, Jiaxun Yang, Aleksandar Rikalo, Riku Voipio, Daniel P. Berrangé, Huacai Chen, Aurelien Jarno On 09/10/2025 21.52, Philippe Mathieu-Daudé wrote: > See previous commit for rationale. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > meson.build | 2 -- > 1 file changed, 2 deletions(-) > > diff --git a/meson.build b/meson.build > index afaefa01722..c5710a6a47c 100644 > --- a/meson.build > +++ b/meson.build > @@ -295,8 +295,6 @@ elif cpu == 'ppc' > kvm_targets = ['ppc-softmmu'] > elif cpu == 'ppc64' > kvm_targets = ['ppc-softmmu', 'ppc64-softmmu'] > -elif cpu == 'mips' > - kvm_targets = ['mips-softmmu', 'mipsel-softmmu'] > elif cpu == 'mips64' > kvm_targets = ['mips-softmmu', 'mipsel-softmmu', 'mips64-softmmu', 'mips64el-softmmu'] > elif cpu == 'riscv32' Reviewed-by: Thomas Huth <thuth@redhat.com> ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 7/7] buildsys: Remove support for 32-bit MIPS hosts 2025-10-09 19:52 [PATCH v2 0/7] tcg/mips: Remove support for 32-bit hosts Philippe Mathieu-Daudé ` (5 preceding siblings ...) 2025-10-09 19:52 ` [PATCH v2 6/7] kvm/mips: " Philippe Mathieu-Daudé @ 2025-10-09 19:52 ` Philippe Mathieu-Daudé 2025-10-10 6:53 ` Thomas Huth 2025-10-10 8:46 ` Daniel P. Berrangé 6 siblings, 2 replies; 14+ messages in thread From: Philippe Mathieu-Daudé @ 2025-10-09 19:52 UTC (permalink / raw) To: qemu-devel Cc: Alex Bennée, Thomas Huth, Paolo Bonzini, Richard Henderson, Marc-André Lureau, Philippe Mathieu-Daudé, devel, Jiaxun Yang, Aleksandar Rikalo, Riku Voipio, Daniel P. Berrangé, Huacai Chen, Aurelien Jarno Stop detecting 32-bit MIPS host as supported, update the deprecation document. See previous commit for rationale. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- docs/about/deprecated.rst | 13 +++++-------- docs/about/removed-features.rst | 6 ++++++ configure | 7 ------- 3 files changed, 11 insertions(+), 15 deletions(-) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index 67e527740c0..79cc34cfeb6 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -172,17 +172,14 @@ This argument has always been ignored. Host Architectures ------------------ -Big endian MIPS since 7.2; 32-bit little endian MIPS since 9.2, MIPS since 11.0 -''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' +MIPS (since 11.0) +''''''''''''''''' -As Debian 10 ("Buster") moved into LTS the big endian 32 bit version of -MIPS moved out of support making it hard to maintain our -cross-compilation CI tests of the architecture. As we no longer have -CI coverage support may bitrot away before the deprecation process +MIPS is not supported by Debian 13 ("Trixie") and newer, making it hard to +maintain our cross-compilation CI tests of the architecture. As we no longer +have CI coverage support may bitrot away before the deprecation process completes. -Likewise, MIPS is not supported by Debian 13 ("Trixie") and newer. - System emulation on 32-bit x86 hosts (since 8.0) '''''''''''''''''''''''''''''''''''''''''''''''' diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.rst index a5338e44c24..53829f59e65 100644 --- a/docs/about/removed-features.rst +++ b/docs/about/removed-features.rst @@ -896,6 +896,12 @@ work around the atomicity issues in system mode by running all vCPUs in a single thread context; in user mode atomicity was simply broken. From 10.0, QEMU has disabled configuration of 64-bit guests on 32-bit hosts. +32-bit MIPS (since 11.0) +'''''''''''''''''''''''' + +Debian 12 "Bookworm" removed support for 32-bit MIPS, making it hard to +maintain our cross-compilation CI tests of the architecture. + Guest Emulator ISAs ------------------- diff --git a/configure b/configure index 6a633ac2b16..8236f43e8f9 100755 --- a/configure +++ b/configure @@ -404,8 +404,6 @@ elif check_define _ARCH_PPC ; then elif check_define __mips__ ; then if check_define __mips64 ; then cpu="mips64" - else - cpu="mips" fi elif check_define __s390__ ; then if check_define __s390x__ ; then @@ -473,11 +471,6 @@ case "$cpu" in host_arch=mips linux_arch=mips ;; - mips*) - cpu=mips - host_arch=mips - linux_arch=mips - ;; ppc) host_arch=ppc -- 2.51.0 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v2 7/7] buildsys: Remove support for 32-bit MIPS hosts 2025-10-09 19:52 ` [PATCH v2 7/7] buildsys: Remove support for 32-bit MIPS hosts Philippe Mathieu-Daudé @ 2025-10-10 6:53 ` Thomas Huth 2025-10-10 8:46 ` Daniel P. Berrangé 1 sibling, 0 replies; 14+ messages in thread From: Thomas Huth @ 2025-10-10 6:53 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel Cc: Alex Bennée, Paolo Bonzini, Richard Henderson, Marc-André Lureau, devel, Jiaxun Yang, Aleksandar Rikalo, Riku Voipio, Daniel P. Berrangé, Huacai Chen, Aurelien Jarno On 09/10/2025 21.52, Philippe Mathieu-Daudé wrote: > Stop detecting 32-bit MIPS host as supported, update the > deprecation document. See previous commit for rationale. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > docs/about/deprecated.rst | 13 +++++-------- > docs/about/removed-features.rst | 6 ++++++ > configure | 7 ------- > 3 files changed, 11 insertions(+), 15 deletions(-) > > diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst > index 67e527740c0..79cc34cfeb6 100644 > --- a/docs/about/deprecated.rst > +++ b/docs/about/deprecated.rst > @@ -172,17 +172,14 @@ This argument has always been ignored. > Host Architectures > ------------------ > > -Big endian MIPS since 7.2; 32-bit little endian MIPS since 9.2, MIPS since 11.0 > -''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' > +MIPS (since 11.0) > +''''''''''''''''' > > -As Debian 10 ("Buster") moved into LTS the big endian 32 bit version of > -MIPS moved out of support making it hard to maintain our > -cross-compilation CI tests of the architecture. As we no longer have > -CI coverage support may bitrot away before the deprecation process > +MIPS is not supported by Debian 13 ("Trixie") and newer, making it hard to > +maintain our cross-compilation CI tests of the architecture. As we no longer > +have CI coverage support may bitrot away before the deprecation process > completes. > > -Likewise, MIPS is not supported by Debian 13 ("Trixie") and newer. > - > System emulation on 32-bit x86 hosts (since 8.0) > '''''''''''''''''''''''''''''''''''''''''''''''' > > diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.rst > index a5338e44c24..53829f59e65 100644 > --- a/docs/about/removed-features.rst > +++ b/docs/about/removed-features.rst > @@ -896,6 +896,12 @@ work around the atomicity issues in system mode by running all vCPUs > in a single thread context; in user mode atomicity was simply broken. > From 10.0, QEMU has disabled configuration of 64-bit guests on 32-bit hosts. > > +32-bit MIPS (since 11.0) > +'''''''''''''''''''''''' > + > +Debian 12 "Bookworm" removed support for 32-bit MIPS, making it hard to > +maintain our cross-compilation CI tests of the architecture. > + > Guest Emulator ISAs > ------------------- > > diff --git a/configure b/configure > index 6a633ac2b16..8236f43e8f9 100755 > --- a/configure > +++ b/configure > @@ -404,8 +404,6 @@ elif check_define _ARCH_PPC ; then > elif check_define __mips__ ; then > if check_define __mips64 ; then > cpu="mips64" > - else > - cpu="mips" > fi > elif check_define __s390__ ; then > if check_define __s390x__ ; then > @@ -473,11 +471,6 @@ case "$cpu" in > host_arch=mips > linux_arch=mips > ;; > - mips*) > - cpu=mips > - host_arch=mips > - linux_arch=mips > - ;; > > ppc) > host_arch=ppc Reviewed-by: Thomas Huth <thuth@redhat.com> ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 7/7] buildsys: Remove support for 32-bit MIPS hosts 2025-10-09 19:52 ` [PATCH v2 7/7] buildsys: Remove support for 32-bit MIPS hosts Philippe Mathieu-Daudé 2025-10-10 6:53 ` Thomas Huth @ 2025-10-10 8:46 ` Daniel P. Berrangé 2025-10-10 10:39 ` Philippe Mathieu-Daudé 1 sibling, 1 reply; 14+ messages in thread From: Daniel P. Berrangé @ 2025-10-10 8:46 UTC (permalink / raw) To: Philippe Mathieu-Daudé Cc: qemu-devel, Alex Bennée, Thomas Huth, Paolo Bonzini, Richard Henderson, Marc-André Lureau, devel, Jiaxun Yang, Aleksandar Rikalo, Riku Voipio, Huacai Chen, Aurelien Jarno On Thu, Oct 09, 2025 at 09:52:10PM +0200, Philippe Mathieu-Daudé wrote: > Stop detecting 32-bit MIPS host as supported, update the > deprecation document. See previous commit for rationale. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > docs/about/deprecated.rst | 13 +++++-------- > docs/about/removed-features.rst | 6 ++++++ > configure | 7 ------- > 3 files changed, 11 insertions(+), 15 deletions(-) > > diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst > index 67e527740c0..79cc34cfeb6 100644 > --- a/docs/about/deprecated.rst > +++ b/docs/about/deprecated.rst > @@ -172,17 +172,14 @@ This argument has always been ignored. > Host Architectures > ------------------ > > -Big endian MIPS since 7.2; 32-bit little endian MIPS since 9.2, MIPS since 11.0 Did 'Big endian MIPS' refer to 32-bit, or both 32 & 64-bit ? I'm guessing it was only 32-bit BE, given the heading of your removed-features.txt change. But then did "MIPS since 11.0" refer to 64-bit little endian only, or both big & little endian for 64-bit ? Given the wide variety of things all ambiguously called "MIPS", its worth being explicit.... > -''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' > +MIPS (since 11.0) > +''''''''''''''''' ...so if this is 64-bit MIPS, big & little endian, lets say so > > -As Debian 10 ("Buster") moved into LTS the big endian 32 bit version of > -MIPS moved out of support making it hard to maintain our > -cross-compilation CI tests of the architecture. As we no longer have > -CI coverage support may bitrot away before the deprecation process > +MIPS is not supported by Debian 13 ("Trixie") and newer, making it hard to > +maintain our cross-compilation CI tests of the architecture. As we no longer > +have CI coverage support may bitrot away before the deprecation process > completes. > > -Likewise, MIPS is not supported by Debian 13 ("Trixie") and newer. > - > System emulation on 32-bit x86 hosts (since 8.0) > '''''''''''''''''''''''''''''''''''''''''''''''' > > diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.rst > index a5338e44c24..53829f59e65 100644 > --- a/docs/about/removed-features.rst > +++ b/docs/about/removed-features.rst > @@ -896,6 +896,12 @@ work around the atomicity issues in system mode by running all vCPUs > in a single thread context; in user mode atomicity was simply broken. > From 10.0, QEMU has disabled configuration of 64-bit guests on 32-bit hosts. > > +32-bit MIPS (since 11.0) > +'''''''''''''''''''''''' > + > +Debian 12 "Bookworm" removed support for 32-bit MIPS, making it hard to > +maintain our cross-compilation CI tests of the architecture. > + > Guest Emulator ISAs > ------------------- > > diff --git a/configure b/configure > index 6a633ac2b16..8236f43e8f9 100755 > --- a/configure > +++ b/configure > @@ -404,8 +404,6 @@ elif check_define _ARCH_PPC ; then > elif check_define __mips__ ; then > if check_define __mips64 ; then > cpu="mips64" > - else > - cpu="mips" > fi > elif check_define __s390__ ; then > if check_define __s390x__ ; then > @@ -473,11 +471,6 @@ case "$cpu" in > host_arch=mips > linux_arch=mips > ;; > - mips*) > - cpu=mips > - host_arch=mips > - linux_arch=mips > - ;; > > ppc) > host_arch=ppc > -- > 2.51.0 > With regards, Daniel -- |: https://berrange.com -o- https://www.flickr.com/photos/dberrange :| |: https://libvirt.org -o- https://fstop138.berrange.com :| |: https://entangle-photo.org -o- https://www.instagram.com/dberrange :| ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 7/7] buildsys: Remove support for 32-bit MIPS hosts 2025-10-10 8:46 ` Daniel P. Berrangé @ 2025-10-10 10:39 ` Philippe Mathieu-Daudé 0 siblings, 0 replies; 14+ messages in thread From: Philippe Mathieu-Daudé @ 2025-10-10 10:39 UTC (permalink / raw) To: Daniel P. Berrangé Cc: qemu-devel, Alex Bennée, Thomas Huth, Paolo Bonzini, Richard Henderson, Marc-André Lureau, devel, Jiaxun Yang, Aleksandar Rikalo, Riku Voipio, Huacai Chen, Aurelien Jarno On 10/10/25 10:46, Daniel P. Berrangé wrote: > On Thu, Oct 09, 2025 at 09:52:10PM +0200, Philippe Mathieu-Daudé wrote: >> Stop detecting 32-bit MIPS host as supported, update the >> deprecation document. See previous commit for rationale. >> >> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> >> --- >> docs/about/deprecated.rst | 13 +++++-------- >> docs/about/removed-features.rst | 6 ++++++ >> configure | 7 ------- >> 3 files changed, 11 insertions(+), 15 deletions(-) >> >> diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst >> index 67e527740c0..79cc34cfeb6 100644 >> --- a/docs/about/deprecated.rst >> +++ b/docs/about/deprecated.rst >> @@ -172,17 +172,14 @@ This argument has always been ignored. >> Host Architectures >> ------------------ >> >> -Big endian MIPS since 7.2; 32-bit little endian MIPS since 9.2, MIPS since 11.0 > > Did 'Big endian MIPS' refer to 32-bit, or both 32 & 64-bit ? I'm guessing > it was only 32-bit BE, given the heading of your removed-features.txt > change. Both. * 7.2 deprecated: - 32-bit big endian MIPS host - 64-bit big endian MIPS host Not deprecated remaining: - 32-bit little endian MIPS host - 64-bit little endian MIPS host * 9.2 deprecated: - 32-bit little endian MIPS host Not deprecated remaining: - 64-bit little endian MIPS host * 11.0 deprecated: - 64-bit little endian MIPS host No non-deprecated MIPS host remaining As of 11.0 we can remove what was deprecated previous 10.1. > > But then did "MIPS since 11.0" refer to 64-bit little endian only, or > both big & little endian for 64-bit ? > > Given the wide variety of things all ambiguously called "MIPS", > its worth being explicit.... > >> -''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' >> +MIPS (since 11.0) >> +''''''''''''''''' > > ...so if this is 64-bit MIPS, big & little endian, lets say so I'll update to "64-bit little endian MIPS". > >> >> -As Debian 10 ("Buster") moved into LTS the big endian 32 bit version of >> -MIPS moved out of support making it hard to maintain our >> -cross-compilation CI tests of the architecture. As we no longer have >> -CI coverage support may bitrot away before the deprecation process >> +MIPS is not supported by Debian 13 ("Trixie") and newer, making it hard to >> +maintain our cross-compilation CI tests of the architecture. As we no longer >> +have CI coverage support may bitrot away before the deprecation process >> completes. >> >> -Likewise, MIPS is not supported by Debian 13 ("Trixie") and newer. >> - >> System emulation on 32-bit x86 hosts (since 8.0) >> '''''''''''''''''''''''''''''''''''''''''''''''' >> >> diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.rst >> index a5338e44c24..53829f59e65 100644 >> --- a/docs/about/removed-features.rst >> +++ b/docs/about/removed-features.rst >> @@ -896,6 +896,12 @@ work around the atomicity issues in system mode by running all vCPUs >> in a single thread context; in user mode atomicity was simply broken. >> From 10.0, QEMU has disabled configuration of 64-bit guests on 32-bit hosts. >> >> +32-bit MIPS (since 11.0) >> +'''''''''''''''''''''''' >> + >> +Debian 12 "Bookworm" removed support for 32-bit MIPS, making it hard to >> +maintain our cross-compilation CI tests of the architecture. >> + >> Guest Emulator ISAs >> ------------------- ^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2025-10-10 10:40 UTC | newest] Thread overview: 14+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-10-09 19:52 [PATCH v2 0/7] tcg/mips: Remove support for 32-bit hosts Philippe Mathieu-Daudé 2025-10-09 19:52 ` [PATCH v2 1/7] docker: Remove 32-bit MIPS toolchain from debian-all-test image Philippe Mathieu-Daudé 2025-10-09 19:52 ` [PATCH v2 2/7] gitlab: Stop cross-testing for 32-bit MIPS hosts Philippe Mathieu-Daudé 2025-10-09 19:52 ` [PATCH v2 3/7] docker: Stop building 32-bit MIPS images Philippe Mathieu-Daudé 2025-10-09 19:52 ` [PATCH v2 4/7] tcg/mips: Remove support for O32 and N32 ABIs Philippe Mathieu-Daudé 2025-10-10 6:45 ` Thomas Huth 2025-10-09 19:52 ` [PATCH v2 5/7] tcg/mips: Remove support for 32-bit hosts Philippe Mathieu-Daudé 2025-10-10 6:51 ` Thomas Huth 2025-10-09 19:52 ` [PATCH v2 6/7] kvm/mips: " Philippe Mathieu-Daudé 2025-10-10 6:52 ` Thomas Huth 2025-10-09 19:52 ` [PATCH v2 7/7] buildsys: Remove support for 32-bit MIPS hosts Philippe Mathieu-Daudé 2025-10-10 6:53 ` Thomas Huth 2025-10-10 8:46 ` Daniel P. Berrangé 2025-10-10 10:39 ` Philippe Mathieu-Daudé
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