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([2001:ee0:50f4:9050:647f:b391:99d7:635d]) by smtp.gmail.com with ESMTPSA id i17-20020a17090332d100b001c32fd9e412sm7523278plr.58.2023.10.24.08.27.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 24 Oct 2023 08:27:32 -0700 (PDT) Message-ID: Date: Tue, 24 Oct 2023 22:27:25 +0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 1/5] i386/tcg: implement x2APIC registers MSR access To: Phil Dennis-Jordan Cc: qemu-devel@nongnu.org, David Woodhouse , Paolo Bonzini , Richard Henderson , Eduardo Habkost , "Michael S . Tsirkin" , Marcel Apfelbaum , Igor Mammedov , =?UTF-8?Q?Alex_Benn=C3=A9e?= , Joao Martins , Peter Xu , Jason Wang , =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= References: <20230926160637.27995-1-minhquangbui99@gmail.com> <20230926160637.27995-2-minhquangbui99@gmail.com> Content-Language: en-US From: Bui Quang Minh In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=minhquangbui99@gmail.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 10/22/23 20:59, Phil Dennis-Jordan wrote: > I can confirm that this works. The build issue obviously needs fixing, > but once that's fixed, this improves on the status quo. > > I've tested this and patch 2/5 with x2apic CPUID bit enabled with the > hvf backend on macOS. To make it work in hvf mode, I used the attached > additional minimal patch to wire it up, but with that in place it > noticeably improves guest OS performance. (This patch doesn't yet > implement raising exceptions or checking for x2apic mode, more on that > in my comments below.) > > Reviewed-by: Phil Dennis-Jordan > > On Tue, 26 Sept 2023 at 18:08, Bui Quang Minh wrote: >> @@ -455,6 +469,19 @@ void helper_rdmsr(CPUX86State *env) >> val = (cs->nr_threads * cs->nr_cores) | (cs->nr_cores << 16); >> break; >> } >> + case MSR_APIC_START ... MSR_APIC_END: { >> + int index = (uint32_t)env->regs[R_ECX] - MSR_APIC_START; >> + >> + if (!is_x2apic_mode(env_archcpu(env)->apic_state)) { >> + raise_exception_ra(env, EXCP0D_GPF, GETPC()); >> + } >> + >> + qemu_mutex_lock_iothread(); >> + val = apic_register_read(index); >> + qemu_mutex_unlock_iothread(); > > Shouldn't the x2apic mode check technically be inside the lock? > Furthermore, we need the mode check logic in each accelerator whose > MSR read and write we wire up. Finally, there's the exception raising > issue which Michael noted. > > So my suggestion would be to wrap the x2apic mode check and the call > to the lower level apic_register_read into a standalone > apic_x2apic_msr_read() or similar, and the equivalent for writes. > These functions should then also return success or failure, the latter > indicating an exception should be raised. Raising the exception can > then also be implemented for each accelerator at the relevant call > site. That contains the raise_exception_ra call in the TCG specific > code, and I can do the equivalent on the hvf side. Thanks a lot for your suggestion, I've taken this approach and implemented an apic_msr_read/write wrapper as you suggested in version 9 (https://lore.kernel.org/qemu-devel/20231024152105.35942-1-minhquangbui99@gmail.com/) Thank you, Quang Minh.