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X-Received-From: 2607:f8b0:4864:20::243 Subject: Re: [Qemu-devel] [PATCH 34/42] target/arm: Convert the VCVT-from-f16 insns to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 6/6/19 12:46 PM, Peter Maydell wrote: > Convert the VCVTT, VCVTB instructions that deal with conversion > from half-precision floats to f32 or 64 to decodetree. > > Since we're no longer constrained to the old decoder's style > using cpu_F0s and cpu_F0d we can perform a direct 16 bit > load of the right half of the input single-precision register > rather than loading the full 32 bits and then doing a > separate shift or sign-extension. > > Signed-off-by: Peter Maydell > --- > target/arm/translate-vfp.inc.c | 82 ++++++++++++++++++++++++++++++++++ > target/arm/translate.c | 56 +---------------------- > target/arm/vfp.decode | 6 +++ > 3 files changed, 89 insertions(+), 55 deletions(-) Reviewed-by: Richard Henderson r~