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[59.100.211.22]) by smtp.gmail.com with ESMTPSA id c26sm64615241pfj.101.2020.01.03.15.05.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 03 Jan 2020 15:05:39 -0800 (PST) Subject: Re: [PATCH v3 1/4] RISC-V: add vector extension field in CPURISCVState To: LIU Zhiwei , alistair23@gmail.com, chihmin.chao@sifive.com, palmer@dabbelt.com References: <20200103033347.20909-1-zhiwei_liu@c-sky.com> <20200103033347.20909-2-zhiwei_liu@c-sky.com> From: Richard Henderson Message-ID: Date: Sat, 4 Jan 2020 10:05:32 +1100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20200103033347.20909-2-zhiwei_liu@c-sky.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wenmeng_zhang@c-sky.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, wxy194768@alibaba-inc.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 1/3/20 2:33 PM, LIU Zhiwei wrote: > The 32 vector registers will be viewed as a continuous memory block. > It avoids the convension between element index and (regno,offset). > Thus elements can be directly accessed by offset from the first vector > base address. > > Signed-off-by: LIU Zhiwei > --- > target/riscv/cpu.h | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 0adb307f32..af66674461 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -93,9 +93,23 @@ typedef struct CPURISCVState CPURISCVState; > > #include "pmp.h" > > +#define RV_VLEN_MAX 4096 > + > struct CPURISCVState { > target_ulong gpr[32]; > uint64_t fpr[32]; /* assume both F and D extensions */ > + > + /* vector coprocessor state. */ > + struct { > + uint64_t vreg[32 * RV_VLEN_MAX / 64]; Missing alignment. > + target_ulong vxrm; > + target_ulong vxsat; > + target_ulong vl; > + target_ulong vstart; > + target_ulong vtype; > + } vext; > + > + bool foflag; Remove this. As discussed before, you don't need it. Faulting behaviour should be handled with the proper interfaces. r~