From: Frederic Barrat <fbarrat@linux.ibm.com>
To: "Joel Stanley" <joel@jms.id.au>,
"Cédric Le Goater" <clg@kaod.org>,
"Nicholas Piggin" <npiggin@gmail.com>
Cc: qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Subject: Re: [PATCH v2 4/5] ppc/pnv: Add P10 core xscom model
Date: Tue, 4 Jul 2023 12:12:18 +0200 [thread overview]
Message-ID: <f887812d-a292-ec77-dfa3-838309b95465@linux.ibm.com> (raw)
In-Reply-To: <20230704054204.168547-5-joel@jms.id.au>
On 04/07/2023 07:42, Joel Stanley wrote:
> Like the quad xscoms, add a core model for P10 to allow future
> differentiation from P9.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Fred
> hw/ppc/pnv_core.c | 44 ++++++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 42 insertions(+), 2 deletions(-)
>
> diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
> index e4df435b15e9..1eec28c88c41 100644
> --- a/hw/ppc/pnv_core.c
> +++ b/hw/ppc/pnv_core.c
> @@ -167,6 +167,47 @@ static const MemoryRegionOps pnv_core_power9_xscom_ops = {
> .endianness = DEVICE_BIG_ENDIAN,
> };
>
> +/*
> + * POWER10 core controls
> + */
> +
> +static uint64_t pnv_core_power10_xscom_read(void *opaque, hwaddr addr,
> + unsigned int width)
> +{
> + uint32_t offset = addr >> 3;
> + uint64_t val = 0;
> +
> + switch (offset) {
> + default:
> + qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
> + addr);
> + }
> +
> + return val;
> +}
> +
> +static void pnv_core_power10_xscom_write(void *opaque, hwaddr addr,
> + uint64_t val, unsigned int width)
> +{
> + uint32_t offset = addr >> 3;
> +
> + switch (offset) {
> + default:
> + qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n",
> + addr);
> + }
> +}
> +
> +static const MemoryRegionOps pnv_core_power10_xscom_ops = {
> + .read = pnv_core_power10_xscom_read,
> + .write = pnv_core_power10_xscom_write,
> + .valid.min_access_size = 8,
> + .valid.max_access_size = 8,
> + .impl.min_access_size = 8,
> + .impl.max_access_size = 8,
> + .endianness = DEVICE_BIG_ENDIAN,
> +};
> +
> static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **errp)
> {
> CPUPPCState *env = &cpu->env;
> @@ -315,8 +356,7 @@ static void pnv_core_power10_class_init(ObjectClass *oc, void *data)
> {
> PnvCoreClass *pcc = PNV_CORE_CLASS(oc);
>
> - /* TODO: Use the P9 XSCOMs for now on P10 */
> - pcc->xscom_ops = &pnv_core_power9_xscom_ops;
> + pcc->xscom_ops = &pnv_core_power10_xscom_ops;
> }
>
> static void pnv_core_class_init(ObjectClass *oc, void *data)
next prev parent reply other threads:[~2023-07-04 10:12 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-04 5:41 [PATCH v2 0/5] ppc/pnv: Extend "quad" model for p10 Joel Stanley
2023-07-04 5:42 ` [PATCH v2 1/5] ppc/pnv: quad xscom callbacks are P9 specific Joel Stanley
2023-07-04 9:59 ` Frederic Barrat
2023-07-04 5:42 ` [PATCH v2 2/5] ppc/pnv: Subclass quad xscom callbacks Joel Stanley
2023-07-04 9:59 ` Frederic Barrat
2023-07-04 5:42 ` [PATCH v2 3/5] ppc/pnv: Add P10 quad xscom model Joel Stanley
2023-07-04 6:55 ` Cédric Le Goater
2023-07-04 10:11 ` Frederic Barrat
2023-07-04 5:42 ` [PATCH v2 4/5] ppc/pnv: Add P10 core " Joel Stanley
2023-07-04 6:55 ` Cédric Le Goater
2023-07-04 10:12 ` Frederic Barrat [this message]
2023-07-04 5:42 ` [PATCH v2 5/5] ppc/pnv: Return zero for core thread state xscom Joel Stanley
2023-07-04 10:12 ` Frederic Barrat
2023-07-04 23:12 ` [PATCH v2 0/5] ppc/pnv: Extend "quad" model for p10 Daniel Henrique Barboza
2023-07-05 1:15 ` Nicholas Piggin
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