From: Richard Henderson <richard.henderson@linaro.org>
To: Robert Hoo <robert.hu@linux.intel.com>,
qemu-devel@nongnu.org, pbonzini@redhat.com, laurent@vivier.eu,
philmd@redhat.com, berrange@redhat.com
Cc: robert.hu@intel.com, chao.p.peng@intel.com
Subject: Re: [PATCH v3 2/2] util: add util function buffer_zero_avx512()
Date: Fri, 28 Feb 2020 18:09:14 -0800 [thread overview]
Message-ID: <f8a87ddf-7d51-c9e4-6122-a9e3c1b84c29@linaro.org> (raw)
In-Reply-To: <1582856696-45663-3-git-send-email-robert.hu@linux.intel.com>
On 2/27/20 6:24 PM, Robert Hoo wrote:
> if ((bv & 6) == 6 && (b & bit_AVX2)) {
> cache |= CACHE_AVX2;
> }
> + if ((bv & 6) == 6 && (b & bit_AVX512F)) {
> + cache |= CACHE_AVX512F;
> + }
Oh, one more thing I missed -- we have to ensure that the 512-bit registers are
enabled. I believe the minimum is bits 6 and 7 enabled (ZMM_Hi256, Hi16_ZMM),
since we don't know that the compiler won't allocate registers from zmm16-31.
So: (bv & 0xc6) == 0xc6.
You'd be right that some comments would be helpful on these lines. :-P
With that,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2020-02-29 2:10 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-28 2:24 [PATCH v3 0/2] Add AVX512F optimization option and buffer_zero_avx512() Robert Hoo
2020-02-28 2:24 ` [PATCH v3 1/2] configure: add configure option avx512f_opt Robert Hoo
2020-02-29 1:54 ` Richard Henderson
2020-02-28 2:24 ` [PATCH v3 2/2] util: add util function buffer_zero_avx512() Robert Hoo
2020-02-29 2:09 ` Richard Henderson [this message]
2020-02-29 3:01 ` Robert Hoo
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