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([2602:ae:1547:e101:4ae9:ceee:85cc:a70c]) by smtp.gmail.com with ESMTPSA id bg3-20020a1709028e8300b001616723b8ddsm11263101plb.45.2022.05.31.07.59.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 31 May 2022 07:59:31 -0700 (PDT) Message-ID: Date: Tue, 31 May 2022 07:59:29 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Subject: Re: [PATCH v5 10/17] target/m68k: Implement TRAPcc Content-Language: en-US To: Laurent Vivier Cc: qemu-devel@nongnu.org, Mark Cave-Ayland References: <20220527164807.135038-1-richard.henderson@linaro.org> <20220527164807.135038-11-richard.henderson@linaro.org> <34af03f0-6c53-17a3-b91f-d368fd2ef7c3@vivier.eu> From: Richard Henderson In-Reply-To: <34af03f0-6c53-17a3-b91f-d368fd2ef7c3@vivier.eu> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 5/31/22 01:01, Laurent Vivier wrote: > Le 27/05/2022 à 18:48, Richard Henderson a écrit : >> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/754 >> Reviewed-by: Laurent Vivier >> Signed-off-by: Richard Henderson >> --- >>   target/m68k/cpu.h          |  2 ++ >>   linux-user/m68k/cpu_loop.c |  1 + >>   target/m68k/cpu.c          |  1 + >>   target/m68k/op_helper.c    |  6 +---- >>   target/m68k/translate.c    | 49 ++++++++++++++++++++++++++++++++++++++ >>   5 files changed, 54 insertions(+), 5 deletions(-) >> > ... >> diff --git a/target/m68k/translate.c b/target/m68k/translate.c >> index 399d9232e4..c4fe8abc03 100644 >> --- a/target/m68k/translate.c >> +++ b/target/m68k/translate.c > ... >> @@ -6050,6 +6098,7 @@ void register_m68k_insns (CPUM68KState *env) >>       INSN(scc,       50c0, f0f8, CF_ISA_A); /* Scc.B Dx   */ >>       INSN(scc,       50c0, f0c0, M68000);   /* Scc.B */ >>       INSN(dbcc,      50c8, f0f8, M68000); >> +    INSN(trapcc,    50f8, f0f8, TRAPCC); >>       INSN(tpf,       51f8, fff8, CF_ISA_A); >>       /* Branch instructions.  */ > > This one breaks Mark's series to support MacOS. > > I think the new opcode short-circuits Scc one: > >   ---------------- >   IN: INITRSRCMGR >   0x408011d0:  st 0xa58 >   Disassembler disagrees with translator over instruction decoding >   Please report this to qemu-devel@nongnu.org > > The following patch seems to fix the problem: > > diff --git a/target/m68k/translate.c b/target/m68k/translate.c > index d5d73401b7cc..3b0e3d0b58f6 100644 > --- a/target/m68k/translate.c > +++ b/target/m68k/translate.c > @@ -6119,9 +6119,9 @@ void register_m68k_insns (CPUM68KState *env) >      INSN(addsubq,   5000, f080, M68000); >      BASE(addsubq,   5080, f0c0); >      INSN(scc,       50c0, f0f8, CF_ISA_A); /* Scc.B Dx   */ > +    INSN(trapcc,    50f8, f0f8, TRAPCC); >      INSN(scc,       50c0, f0c0, M68000);   /* Scc.B */ >      INSN(dbcc,      50c8, f0f8, M68000); > -    INSN(trapcc,    50f8, f0f8, TRAPCC); Hmm. That will completely hide trapcc -- you should have seen the new test case fail (and if not, the test case needs fixing). These two insn overlap considerably: setcc 0101 cond:4 11 mode:3 reg:3 trapcc 0101 cond:4 11 111 opmode:3 We need to select only the 3 valid opmodes: INSN(scc, 50c0, f0c0, M68000); /* Scc.B */ INSN(dbcc, 50c8, f0f8, M68000); INSN(trapcc, 50fa, f0fe, TRAPCC); /* opmode 010, 011 */ INSN(trapcc, 50fc, f0ff, TRAPCC); /* opmode 100 */ INSN(trapcc, 51fa, fffe, CP_ISA_A); /* TPF (trapf) opmode 010, 011 */ INSN(trapcc, 51fc, ffff, CP_ISA_A); /* TPF (trapf) opmode 100 */ which are invalid mode/reg combinations for Scc. r~