* [PATCH 01/10] tests/tcg/tricore: Bump cpu to tc37x
2023-08-26 16:02 [PATCH 00/10] TriCore 1.6.2 insn and bugfixes Bastian Koppelmann
@ 2023-08-26 16:02 ` Bastian Koppelmann
2023-08-27 4:23 ` Richard Henderson
2023-08-26 16:02 ` [PATCH 02/10] target/tricore: Implement CRCN insn Bastian Koppelmann
` (8 subsequent siblings)
9 siblings, 1 reply; 29+ messages in thread
From: Bastian Koppelmann @ 2023-08-26 16:02 UTC (permalink / raw)
To: qemu-devel; +Cc: anton.kochkov, kbastian
we don't want to exclude ISA v1.6.2 insns from our tests.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
tests/tcg/tricore/Makefile.softmmu-target | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/tcg/tricore/Makefile.softmmu-target b/tests/tcg/tricore/Makefile.softmmu-target
index aff7c1b580..f8fd207921 100644
--- a/tests/tcg/tricore/Makefile.softmmu-target
+++ b/tests/tcg/tricore/Makefile.softmmu-target
@@ -25,7 +25,7 @@ TESTS += test_muls.asm.tst
TESTS += test_boot_to_main.c.tst
TESTS += test_context_save_areas.c.tst
-QEMU_OPTS += -M tricore_testboard -cpu tc27x -nographic -kernel
+QEMU_OPTS += -M tricore_testboard -cpu tc37x -nographic -kernel
%.pS: $(ASM_TESTS_PATH)/%.S
$(HOST_CC) -E -o $@ $<
--
2.41.0
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 02/10] target/tricore: Implement CRCN insn
2023-08-26 16:02 [PATCH 00/10] TriCore 1.6.2 insn and bugfixes Bastian Koppelmann
2023-08-26 16:02 ` [PATCH 01/10] tests/tcg/tricore: Bump cpu to tc37x Bastian Koppelmann
@ 2023-08-26 16:02 ` Bastian Koppelmann
2023-08-27 4:33 ` Richard Henderson
2023-08-26 16:02 ` [PATCH 03/10] target/tricore: Correctly handle FPU RM from PSW Bastian Koppelmann
` (7 subsequent siblings)
9 siblings, 1 reply; 29+ messages in thread
From: Bastian Koppelmann @ 2023-08-26 16:02 UTC (permalink / raw)
To: qemu-devel; +Cc: anton.kochkov, kbastian
reported in https://gitlab.com/qemu-project/qemu/-/issues/1667
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/helper.h | 1 +
target/tricore/op_helper.c | 66 +++++++++++++++++++++++
target/tricore/translate.c | 6 +++
target/tricore/tricore-opcodes.h | 1 +
tests/tcg/tricore/Makefile.softmmu-target | 1 +
tests/tcg/tricore/asm/test_crcn.S | 9 ++++
6 files changed, 84 insertions(+)
create mode 100644 tests/tcg/tricore/asm/test_crcn.S
diff --git a/target/tricore/helper.h b/target/tricore/helper.h
index 31d71eac7a..190645413a 100644
--- a/target/tricore/helper.h
+++ b/target/tricore/helper.h
@@ -134,6 +134,7 @@ DEF_HELPER_FLAGS_5(mulr_h, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32, i32, i32)
DEF_HELPER_FLAGS_2(crc32b, TCG_CALL_NO_RWG_SE, i32, i32, i32)
DEF_HELPER_FLAGS_2(crc32_be, TCG_CALL_NO_RWG_SE, i32, i32, i32)
DEF_HELPER_FLAGS_2(crc32_le, TCG_CALL_NO_RWG_SE, i32, i32, i32)
+DEF_HELPER_FLAGS_3(crcn, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32)
DEF_HELPER_FLAGS_2(shuffle, TCG_CALL_NO_RWG_SE, i32, i32, i32)
/* CSA */
DEF_HELPER_2(call, void, env, i32)
diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c
index 89be1ed648..6445fd334b 100644
--- a/target/tricore/op_helper.c
+++ b/target/tricore/op_helper.c
@@ -2308,6 +2308,72 @@ uint32_t helper_crc32_le(uint32_t arg0, uint32_t arg1)
return crc32(arg1, buf, 4);
}
+static uint32_t crc_div(uint32_t crc_in, uint32_t data, uint32_t gen,
+ uint32_t n, uint32_t m)
+{
+ uint32_t i;
+
+ data = data << n;
+ data = deposit32(data, m, 32 - m, 0);
+ for (i = 0; i < m; i++) {
+
+ if (crc_in & (1u << (n - 1))) {
+ crc_in <<= 1;
+ if (data & (1u << (m - 1))) {
+ crc_in++;
+ }
+ crc_in ^= gen;
+ } else {
+ crc_in <<= 1;
+ if (data & (1u << (m - 1))) {
+ crc_in++;
+ }
+ }
+ data <<= 1;
+ data = deposit32(data, m, 32 - m, 0);
+ }
+
+ return crc_in;
+}
+
+uint32_t helper_crcn(uint32_t arg0, uint32_t arg1, uint32_t arg2)
+{
+ uint32_t crc_out, crc_in;
+ uint32_t n = extract32(arg0, 12, 4) + 1;
+ uint32_t gen = extract32(arg0, 16, n);
+ uint32_t inv = extract32(arg0, 9, 1);
+ uint32_t le = extract32(arg0, 8, 1);
+ uint32_t m = extract32(arg0, 0, 3) + 1;
+ uint32_t data = extract32(arg1, 0, m);
+ uint32_t seed = extract32(arg2, 0, n);
+
+ if (le == 1) {
+ if (m == 0) {
+ data = 0;
+ } else {
+ data = revbit32(data) >> (32 - m);
+ }
+ }
+
+ if (inv == 1) {
+ seed = ~seed;
+ }
+
+ if (m > n) {
+ crc_in = (data >> (m - n)) ^ seed;
+ } else {
+ crc_in = (data << (n - m)) ^ seed;
+ }
+
+ crc_out = crc_div(crc_in, data, gen, n, m);
+
+ if (inv) {
+ crc_out = ~crc_out;
+ }
+
+ return deposit32(crc_out, n, 32 - n, 0);
+}
+
uint32_t helper_shuffle(uint32_t arg0, uint32_t arg1)
{
uint32_t resb;
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 1947733870..bb7dad75d6 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -6673,6 +6673,12 @@ static void decode_rrr_divide(DisasContext *ctx)
gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
break;
+ case OPC2_32_RRR_CRCN:
+ if (has_feature(ctx, TRICORE_FEATURE_162)) {
+ gen_helper_crcn(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2],
+ cpu_gpr_d[r3]);
+ }
+ break;
case OPC2_32_RRR_ADD_F:
gen_helper_fadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]);
break;
diff --git a/target/tricore/tricore-opcodes.h b/target/tricore/tricore-opcodes.h
index bc62b73173..f070571665 100644
--- a/target/tricore/tricore-opcodes.h
+++ b/target/tricore/tricore-opcodes.h
@@ -1247,6 +1247,7 @@ enum {
OPC2_32_RRR_SUB_F = 0x03,
OPC2_32_RRR_MADD_F = 0x06,
OPC2_32_RRR_MSUB_F = 0x07,
+ OPC2_32_RRR_CRCN = 0x01, /* 1.6.2 up */
};
/*
* RRR1 Format
diff --git a/tests/tcg/tricore/Makefile.softmmu-target b/tests/tcg/tricore/Makefile.softmmu-target
index f8fd207921..7a7d73a60c 100644
--- a/tests/tcg/tricore/Makefile.softmmu-target
+++ b/tests/tcg/tricore/Makefile.softmmu-target
@@ -9,6 +9,7 @@ CFLAGS = -mtc162 -c -I$(TESTS_PATH)
TESTS += test_abs.asm.tst
TESTS += test_bmerge.asm.tst
TESTS += test_clz.asm.tst
+TESTS += test_crcn.asm.tst
TESTS += test_dextr.asm.tst
TESTS += test_dvstep.asm.tst
TESTS += test_fadd.asm.tst
diff --git a/tests/tcg/tricore/asm/test_crcn.S b/tests/tcg/tricore/asm/test_crcn.S
new file mode 100644
index 0000000000..51a22722a3
--- /dev/null
+++ b/tests/tcg/tricore/asm/test_crcn.S
@@ -0,0 +1,9 @@
+#include "macros.h"
+.text
+.global _start
+_start:
+# insn num result rs1 rs2 rs3
+# | | | | | |
+ TEST_D_DDD(crcn, 1, 0x00002bed, 0x0, 0xa10ddeed, 0x0)
+
+ TEST_PASSFAIL
--
2.41.0
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH 02/10] target/tricore: Implement CRCN insn
2023-08-26 16:02 ` [PATCH 02/10] target/tricore: Implement CRCN insn Bastian Koppelmann
@ 2023-08-27 4:33 ` Richard Henderson
0 siblings, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2023-08-27 4:33 UTC (permalink / raw)
To: Bastian Koppelmann, qemu-devel; +Cc: anton.kochkov
On 8/26/23 09:02, Bastian Koppelmann wrote:
> +static uint32_t crc_div(uint32_t crc_in, uint32_t data, uint32_t gen,
> + uint32_t n, uint32_t m)
> +{
> + uint32_t i;
> +
> + data = data << n;
> + data = deposit32(data, m, 32 - m, 0);
This is data = extract32(data, 0, m), however...
> + for (i = 0; i < m; i++) {
> +
> + if (crc_in & (1u << (n - 1))) {
> + crc_in <<= 1;
> + if (data & (1u << (m - 1))) {
You only check a single bit of data here, always bit m-1.
> + crc_in++;
> + }
> + crc_in ^= gen;
> + } else {
> + crc_in <<= 1;
> + if (data & (1u << (m - 1))) {
> + crc_in++;
> + }
> + }
> + data <<= 1;
> + data = deposit32(data, m, 32 - m, 0);
So why do you need to keep bits above m clear?
I think you should just shift left and let bits fall off the left naturally.
> + return deposit32(crc_out, n, 32 - n, 0);
extract32(crc_out, 0, n);
> +}
> +
> uint32_t helper_shuffle(uint32_t arg0, uint32_t arg1)
> {
> uint32_t resb;
> diff --git a/target/tricore/translate.c b/target/tricore/translate.c
> index 1947733870..bb7dad75d6 100644
> --- a/target/tricore/translate.c
> +++ b/target/tricore/translate.c
> @@ -6673,6 +6673,12 @@ static void decode_rrr_divide(DisasContext *ctx)
> gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3],
> cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
> break;
> + case OPC2_32_RRR_CRCN:
> + if (has_feature(ctx, TRICORE_FEATURE_162)) {
> + gen_helper_crcn(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2],
> + cpu_gpr_d[r3]);
> + }
> + break;
trap if not feature 162.
r~
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 03/10] target/tricore: Correctly handle FPU RM from PSW
2023-08-26 16:02 [PATCH 00/10] TriCore 1.6.2 insn and bugfixes Bastian Koppelmann
2023-08-26 16:02 ` [PATCH 01/10] tests/tcg/tricore: Bump cpu to tc37x Bastian Koppelmann
2023-08-26 16:02 ` [PATCH 02/10] target/tricore: Implement CRCN insn Bastian Koppelmann
@ 2023-08-26 16:02 ` Bastian Koppelmann
2023-08-27 4:37 ` Richard Henderson
2023-08-26 16:02 ` [PATCH 04/10] target/tricore: Implement FTOU insn Bastian Koppelmann
` (6 subsequent siblings)
9 siblings, 1 reply; 29+ messages in thread
From: Bastian Koppelmann @ 2023-08-26 16:02 UTC (permalink / raw)
To: qemu-devel; +Cc: anton.kochkov, kbastian
when we reconstructed PSW using psw_read(), we were trying to clear the
cached USB bits out of env->PSW. The mask was wrong and we would clear
PSW.RM as well.
when we write the PSW using psw_write() we update the rounding modes in
env->fp_status for softfloat. The order of bits used by TriCore is not
the one used by softfloat.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/helper.c | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/target/tricore/helper.c b/target/tricore/helper.c
index 6d076ac36f..e615c3d6d4 100644
--- a/target/tricore/helper.c
+++ b/target/tricore/helper.c
@@ -120,7 +120,21 @@ void tricore_cpu_list(void)
void fpu_set_state(CPUTriCoreState *env)
{
- set_float_rounding_mode(env->PSW & MASK_PSW_FPU_RM, &env->fp_status);
+ switch (extract32(env->PSW, 24, 2)) {
+ case 0:
+ set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
+ break;
+ case 1:
+ set_float_rounding_mode(float_round_up, &env->fp_status);
+ break;
+ case 2:
+ set_float_rounding_mode(float_round_down, &env->fp_status);
+ break;
+ case 3:
+ set_float_rounding_mode(float_round_to_zero, &env->fp_status);
+ break;
+ }
+
set_flush_inputs_to_zero(1, &env->fp_status);
set_flush_to_zero(1, &env->fp_status);
set_default_nan_mode(1, &env->fp_status);
@@ -129,7 +143,7 @@ void fpu_set_state(CPUTriCoreState *env)
uint32_t psw_read(CPUTriCoreState *env)
{
/* clear all USB bits */
- env->PSW &= 0x6ffffff;
+ env->PSW &= 0x7ffffff;
/* now set them from the cache */
env->PSW |= ((env->PSW_USB_C != 0) << 31);
env->PSW |= ((env->PSW_USB_V & (1 << 31)) >> 1);
--
2.41.0
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH 03/10] target/tricore: Correctly handle FPU RM from PSW
2023-08-26 16:02 ` [PATCH 03/10] target/tricore: Correctly handle FPU RM from PSW Bastian Koppelmann
@ 2023-08-27 4:37 ` Richard Henderson
0 siblings, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2023-08-27 4:37 UTC (permalink / raw)
To: Bastian Koppelmann, qemu-devel; +Cc: anton.kochkov
On 8/26/23 09:02, Bastian Koppelmann wrote:
> when we reconstructed PSW using psw_read(), we were trying to clear the
> cached USB bits out of env->PSW. The mask was wrong and we would clear
> PSW.RM as well.
>
> when we write the PSW using psw_write() we update the rounding modes in
> env->fp_status for softfloat. The order of bits used by TriCore is not
> the one used by softfloat.
>
> Signed-off-by: Bastian Koppelmann<kbastian@mail.uni-paderborn.de>
> ---
> target/tricore/helper.c | 18 ++++++++++++++++--
> 1 file changed, 16 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 04/10] target/tricore: Implement FTOU insn
2023-08-26 16:02 [PATCH 00/10] TriCore 1.6.2 insn and bugfixes Bastian Koppelmann
` (2 preceding siblings ...)
2023-08-26 16:02 ` [PATCH 03/10] target/tricore: Correctly handle FPU RM from PSW Bastian Koppelmann
@ 2023-08-26 16:02 ` Bastian Koppelmann
2023-08-27 4:50 ` Richard Henderson
2023-08-26 16:02 ` [PATCH 05/10] target/tricore: Implement ftohp insn Bastian Koppelmann
` (5 subsequent siblings)
9 siblings, 1 reply; 29+ messages in thread
From: Bastian Koppelmann @ 2023-08-26 16:02 UTC (permalink / raw)
To: qemu-devel; +Cc: anton.kochkov, kbastian
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/fpu_helper.c | 25 +++++++++++++++++++++++
target/tricore/helper.h | 1 +
target/tricore/translate.c | 3 +++
tests/tcg/tricore/Makefile.softmmu-target | 1 +
tests/tcg/tricore/asm/test_ftou.S | 12 +++++++++++
5 files changed, 42 insertions(+)
create mode 100644 tests/tcg/tricore/asm/test_ftou.S
diff --git a/target/tricore/fpu_helper.c b/target/tricore/fpu_helper.c
index cb7ee7dd35..ceacb6657e 100644
--- a/target/tricore/fpu_helper.c
+++ b/target/tricore/fpu_helper.c
@@ -429,6 +429,31 @@ uint32_t helper_ftoiz(CPUTriCoreState *env, uint32_t arg)
return result;
}
+uint32_t helper_ftou(CPUTriCoreState *env, uint32_t arg)
+{
+ float32 f_arg = make_float32(arg);
+ uint32_t result;
+ int32_t flags = 0;
+
+ if (float32_is_any_nan(f_arg)) {
+ result = 0;
+ flags |= float_flag_invalid;
+ } else if (float32_lt_quiet(f_arg, 0, &env->fp_status)) {
+ result = 0;
+ flags = float_flag_invalid;
+ } else {
+ result = float32_to_uint32(f_arg, &env->fp_status);
+ flags = f_get_excp_flags(env);
+ }
+
+ if (flags) {
+ f_update_psw_flags(env, flags);
+ } else {
+ env->FPU_FS = 0;
+ }
+ return result;
+}
+
uint32_t helper_ftouz(CPUTriCoreState *env, uint32_t arg)
{
float32 f_arg = make_float32(arg);
diff --git a/target/tricore/helper.h b/target/tricore/helper.h
index 190645413a..827fbaa692 100644
--- a/target/tricore/helper.h
+++ b/target/tricore/helper.h
@@ -114,6 +114,7 @@ DEF_HELPER_2(ftoi, i32, env, i32)
DEF_HELPER_2(itof, i32, env, i32)
DEF_HELPER_2(utof, i32, env, i32)
DEF_HELPER_2(ftoiz, i32, env, i32)
+DEF_HELPER_2(ftou, i32, env, i32)
DEF_HELPER_2(ftouz, i32, env, i32)
DEF_HELPER_2(updfl, void, env, i32)
/* dvinit */
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index bb7dad75d6..fb9a7113a8 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -6273,6 +6273,9 @@ static void decode_rr_divide(DisasContext *ctx)
case OPC2_32_RR_ITOF:
gen_helper_itof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
break;
+ case OPC2_32_RR_FTOU:
+ gen_helper_ftou(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+ break;
case OPC2_32_RR_FTOUZ:
gen_helper_ftouz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
break;
diff --git a/tests/tcg/tricore/Makefile.softmmu-target b/tests/tcg/tricore/Makefile.softmmu-target
index 7a7d73a60c..e6ed5c56f2 100644
--- a/tests/tcg/tricore/Makefile.softmmu-target
+++ b/tests/tcg/tricore/Makefile.softmmu-target
@@ -15,6 +15,7 @@ TESTS += test_dvstep.asm.tst
TESTS += test_fadd.asm.tst
TESTS += test_fmul.asm.tst
TESTS += test_ftoi.asm.tst
+TESTS += test_ftou.asm.tst
TESTS += test_imask.asm.tst
TESTS += test_insert.asm.tst
TESTS += test_ld_bu.asm.tst
diff --git a/tests/tcg/tricore/asm/test_ftou.S b/tests/tcg/tricore/asm/test_ftou.S
new file mode 100644
index 0000000000..10f106ad62
--- /dev/null
+++ b/tests/tcg/tricore/asm/test_ftou.S
@@ -0,0 +1,12 @@
+#include "macros.h"
+.text
+.global _start
+_start:
+ TEST_D_D(ftou, 1, 0x00000000, 0x1733f6c2)
+ TEST_D_D(ftou, 2, 0x00000000, 0x2c9d9cdc)
+ TEST_D_D(ftou, 3, 0xffffffff, 0x56eb7395)
+ TEST_D_D(ftou, 4, 0x79900800, 0x4ef32010)
+ TEST_D_D(ftou, 5, 0x0353f510, 0x4c54fd44)
+
+ TEST_PASSFAIL
+
--
2.41.0
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH 04/10] target/tricore: Implement FTOU insn
2023-08-26 16:02 ` [PATCH 04/10] target/tricore: Implement FTOU insn Bastian Koppelmann
@ 2023-08-27 4:50 ` Richard Henderson
2023-08-27 11:07 ` Bastian Koppelmann
0 siblings, 1 reply; 29+ messages in thread
From: Richard Henderson @ 2023-08-27 4:50 UTC (permalink / raw)
To: Bastian Koppelmann, qemu-devel; +Cc: anton.kochkov
On 8/26/23 09:02, Bastian Koppelmann wrote:
> +uint32_t helper_ftou(CPUTriCoreState *env, uint32_t arg)
> +{
> + float32 f_arg = make_float32(arg);
> + uint32_t result;
> + int32_t flags = 0;
> +
> + if (float32_is_any_nan(f_arg)) {
> + result = 0;
> + flags |= float_flag_invalid;
> + } else if (float32_lt_quiet(f_arg, 0, &env->fp_status)) {
> + result = 0;
> + flags = float_flag_invalid;
> + } else {
> + result = float32_to_uint32(f_arg, &env->fp_status);
> + flags = f_get_excp_flags(env);
> + }
You should allow softfloat to diagnose the special cases, and negative -> 0 is standard
behaviour. Therefore:
result = float32_to_uint32(f_arg, status);
flags = f_get_excp_flags();
if (flags) {
if ((flags & float_flag_invalid)
&& !(get_float_exception_flags() & float_flag_invalid_cvti)) {
/* invalid without cvti is nan input */
result = 0;
}
f_update_psw_flags(...);
} else {
fs = 0;
}
r~
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH 04/10] target/tricore: Implement FTOU insn
2023-08-27 4:50 ` Richard Henderson
@ 2023-08-27 11:07 ` Bastian Koppelmann
2023-08-27 14:49 ` Richard Henderson
0 siblings, 1 reply; 29+ messages in thread
From: Bastian Koppelmann @ 2023-08-27 11:07 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, anton.kochkov
On Sat, Aug 26, 2023 at 09:50:51PM -0700, Richard Henderson wrote:
> On 8/26/23 09:02, Bastian Koppelmann wrote:
> > +uint32_t helper_ftou(CPUTriCoreState *env, uint32_t arg)
> > +{
> > + float32 f_arg = make_float32(arg);
> > + uint32_t result;
> > + int32_t flags = 0;
> > +
> > + if (float32_is_any_nan(f_arg)) {
> > + result = 0;
> > + flags |= float_flag_invalid;
> > + } else if (float32_lt_quiet(f_arg, 0, &env->fp_status)) {
> > + result = 0;
> > + flags = float_flag_invalid;
> > + } else {
> > + result = float32_to_uint32(f_arg, &env->fp_status);
> > + flags = f_get_excp_flags(env);
> > + }
>
> You should allow softfloat to diagnose the special cases, and negative -> 0
> is standard behaviour. Therefore:
You're right. However, there is one special case, negative -> 0 ought to raise
float_flags_invalid. All that has already been done for ftouz, so I will match
that implementation.
Cheers,
Bastian
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH 04/10] target/tricore: Implement FTOU insn
2023-08-27 11:07 ` Bastian Koppelmann
@ 2023-08-27 14:49 ` Richard Henderson
2023-08-27 16:36 ` Bastian Koppelmann
0 siblings, 1 reply; 29+ messages in thread
From: Richard Henderson @ 2023-08-27 14:49 UTC (permalink / raw)
To: Bastian Koppelmann; +Cc: qemu-devel, anton.kochkov
On 8/27/23 04:07, Bastian Koppelmann wrote:
> On Sat, Aug 26, 2023 at 09:50:51PM -0700, Richard Henderson wrote:
>> On 8/26/23 09:02, Bastian Koppelmann wrote:
>>> +uint32_t helper_ftou(CPUTriCoreState *env, uint32_t arg)
>>> +{
>>> + float32 f_arg = make_float32(arg);
>>> + uint32_t result;
>>> + int32_t flags = 0;
>>> +
>>> + if (float32_is_any_nan(f_arg)) {
>>> + result = 0;
>>> + flags |= float_flag_invalid;
>>> + } else if (float32_lt_quiet(f_arg, 0, &env->fp_status)) {
>>> + result = 0;
>>> + flags = float_flag_invalid;
>>> + } else {
>>> + result = float32_to_uint32(f_arg, &env->fp_status);
>>> + flags = f_get_excp_flags(env);
>>> + }
>>
>> You should allow softfloat to diagnose the special cases, and negative -> 0
>> is standard behaviour. Therefore:
>
> You're right. However, there is one special case, negative -> 0 ought to raise
> float_flags_invalid.
https://gitlab.com/qemu-project/qemu/-/blob/master/fpu/softfloat-parts.c.inc?ref_type=heads#L1162
Already done. As I say, this is all standard IEEE behaviour.
r~
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH 04/10] target/tricore: Implement FTOU insn
2023-08-27 14:49 ` Richard Henderson
@ 2023-08-27 16:36 ` Bastian Koppelmann
2023-08-27 18:32 ` Richard Henderson
0 siblings, 1 reply; 29+ messages in thread
From: Bastian Koppelmann @ 2023-08-27 16:36 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, anton.kochkov
On Sun, Aug 27, 2023 at 07:49:52AM -0700, Richard Henderson wrote:
> On 8/27/23 04:07, Bastian Koppelmann wrote:
> > On Sat, Aug 26, 2023 at 09:50:51PM -0700, Richard Henderson wrote:
> > > On 8/26/23 09:02, Bastian Koppelmann wrote:
> > > > +uint32_t helper_ftou(CPUTriCoreState *env, uint32_t arg)
> > > > +{
> > > > + float32 f_arg = make_float32(arg);
> > > > + uint32_t result;
> > > > + int32_t flags = 0;
> > > > +
> > > > + if (float32_is_any_nan(f_arg)) {
> > > > + result = 0;
> > > > + flags |= float_flag_invalid;
> > > > + } else if (float32_lt_quiet(f_arg, 0, &env->fp_status)) {
> > > > + result = 0;
> > > > + flags = float_flag_invalid;
> > > > + } else {
> > > > + result = float32_to_uint32(f_arg, &env->fp_status);
> > > > + flags = f_get_excp_flags(env);
> > > > + }
> > >
> > > You should allow softfloat to diagnose the special cases, and negative -> 0
> > > is standard behaviour. Therefore:
> >
> > You're right. However, there is one special case, negative -> 0 ought to raise
> > float_flags_invalid.
>
> https://gitlab.com/qemu-project/qemu/-/blob/master/fpu/softfloat-parts.c.inc?ref_type=heads#L1162
Lets say the exponent is negative and the sign is negative, then we raise
float_flag_inexact and we never reach the code you mentioned here. However,
TriCore HW raises float_flag_invalid as well in that case. This is what I'm
catching with float32_lt_quiet() in the same manner as ftouz.
Cheers,
Bastian
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH 04/10] target/tricore: Implement FTOU insn
2023-08-27 16:36 ` Bastian Koppelmann
@ 2023-08-27 18:32 ` Richard Henderson
2023-08-27 18:59 ` Bastian Koppelmann
0 siblings, 1 reply; 29+ messages in thread
From: Richard Henderson @ 2023-08-27 18:32 UTC (permalink / raw)
To: Bastian Koppelmann; +Cc: qemu-devel, anton.kochkov
On 8/27/23 09:36, Bastian Koppelmann wrote:
> On Sun, Aug 27, 2023 at 07:49:52AM -0700, Richard Henderson wrote:
>> On 8/27/23 04:07, Bastian Koppelmann wrote:
>>> On Sat, Aug 26, 2023 at 09:50:51PM -0700, Richard Henderson wrote:
>>>> On 8/26/23 09:02, Bastian Koppelmann wrote:
>>>>> +uint32_t helper_ftou(CPUTriCoreState *env, uint32_t arg)
>>>>> +{
>>>>> + float32 f_arg = make_float32(arg);
>>>>> + uint32_t result;
>>>>> + int32_t flags = 0;
>>>>> +
>>>>> + if (float32_is_any_nan(f_arg)) {
>>>>> + result = 0;
>>>>> + flags |= float_flag_invalid;
>>>>> + } else if (float32_lt_quiet(f_arg, 0, &env->fp_status)) {
>>>>> + result = 0;
>>>>> + flags = float_flag_invalid;
>>>>> + } else {
>>>>> + result = float32_to_uint32(f_arg, &env->fp_status);
>>>>> + flags = f_get_excp_flags(env);
>>>>> + }
>>>>
>>>> You should allow softfloat to diagnose the special cases, and negative -> 0
>>>> is standard behaviour. Therefore:
>>>
>>> You're right. However, there is one special case, negative -> 0 ought to raise
>>> float_flags_invalid.
>>
>> https://gitlab.com/qemu-project/qemu/-/blob/master/fpu/softfloat-parts.c.inc?ref_type=heads#L1162
>
> Lets say the exponent is negative and the sign is negative, then we raise
> float_flag_inexact and we never reach the code you mentioned here. However,
> TriCore HW raises float_flag_invalid as well in that case. This is what I'm
> catching with float32_lt_quiet() in the same manner as ftouz.
Hmph. Buggy hardware. You'd better document this special case,
that less-than-zero is detected before rounding.
I presume -0.0 does not raise invalid, that the bug does not extend that far?
r~
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH 04/10] target/tricore: Implement FTOU insn
2023-08-27 18:32 ` Richard Henderson
@ 2023-08-27 18:59 ` Bastian Koppelmann
0 siblings, 0 replies; 29+ messages in thread
From: Bastian Koppelmann @ 2023-08-27 18:59 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, anton.kochkov
On Sun, Aug 27, 2023 at 11:32:03AM -0700, Richard Henderson wrote:
> On 8/27/23 09:36, Bastian Koppelmann wrote:
> > On Sun, Aug 27, 2023 at 07:49:52AM -0700, Richard Henderson wrote:
> > > On 8/27/23 04:07, Bastian Koppelmann wrote:
> > > > On Sat, Aug 26, 2023 at 09:50:51PM -0700, Richard Henderson wrote:
> > > > > On 8/26/23 09:02, Bastian Koppelmann wrote:
> > > > > > +uint32_t helper_ftou(CPUTriCoreState *env, uint32_t arg)
> > > > > > +{
> > > > > > + float32 f_arg = make_float32(arg);
> > > > > > + uint32_t result;
> > > > > > + int32_t flags = 0;
> > > > > > +
> > > > > > + if (float32_is_any_nan(f_arg)) {
> > > > > > + result = 0;
> > > > > > + flags |= float_flag_invalid;
> > > > > > + } else if (float32_lt_quiet(f_arg, 0, &env->fp_status)) {
> > > > > > + result = 0;
> > > > > > + flags = float_flag_invalid;
> > > > > > + } else {
> > > > > > + result = float32_to_uint32(f_arg, &env->fp_status);
> > > > > > + flags = f_get_excp_flags(env);
> > > > > > + }
> > > > >
> > > > > You should allow softfloat to diagnose the special cases, and negative -> 0
> > > > > is standard behaviour. Therefore:
> > > >
> > > > You're right. However, there is one special case, negative -> 0 ought to raise
> > > > float_flags_invalid.
> > >
> > > https://gitlab.com/qemu-project/qemu/-/blob/master/fpu/softfloat-parts.c.inc?ref_type=heads#L1162
> >
> > Lets say the exponent is negative and the sign is negative, then we raise
> > float_flag_inexact and we never reach the code you mentioned here. However,
> > TriCore HW raises float_flag_invalid as well in that case. This is what I'm
> > catching with float32_lt_quiet() in the same manner as ftouz.
>
> Hmph. Buggy hardware. You'd better document this special case,
> that less-than-zero is detected before rounding.
Will do. I'll do the same for ftouz.
>
> I presume -0.0 does not raise invalid, that the bug does not extend that far?
Yes, -0.0 does not raise invalid.
Cheers,
Bastian
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 05/10] target/tricore: Implement ftohp insn
2023-08-26 16:02 [PATCH 00/10] TriCore 1.6.2 insn and bugfixes Bastian Koppelmann
` (3 preceding siblings ...)
2023-08-26 16:02 ` [PATCH 04/10] target/tricore: Implement FTOU insn Bastian Koppelmann
@ 2023-08-26 16:02 ` Bastian Koppelmann
2023-08-27 4:55 ` Richard Henderson
2023-08-26 16:02 ` [PATCH 06/10] target/tricore: Implement hptof insn Bastian Koppelmann
` (4 subsequent siblings)
9 siblings, 1 reply; 29+ messages in thread
From: Bastian Koppelmann @ 2023-08-26 16:02 UTC (permalink / raw)
To: qemu-devel; +Cc: anton.kochkov, kbastian
reported in https://gitlab.com/qemu-project/qemu/-/issues/1667
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/fpu_helper.c | 41 +++++++++++++++++++++++
target/tricore/helper.c | 1 +
target/tricore/helper.h | 1 +
target/tricore/translate.c | 7 ++++
target/tricore/tricore-opcodes.h | 1 +
tests/tcg/tricore/Makefile.softmmu-target | 1 +
tests/tcg/tricore/asm/test_ftohp.S | 14 ++++++++
7 files changed, 66 insertions(+)
create mode 100644 tests/tcg/tricore/asm/test_ftohp.S
diff --git a/target/tricore/fpu_helper.c b/target/tricore/fpu_helper.c
index ceacb6657e..3db2341ac0 100644
--- a/target/tricore/fpu_helper.c
+++ b/target/tricore/fpu_helper.c
@@ -27,6 +27,8 @@
#define SQRT_NAN 0x7fc00004
#define DIV_NAN 0x7fc00008
#define MUL_NAN 0x7fc00002
+#define HP_NEG_INFINITY 0xfc00
+#define HP_POS_INFINITY 0x7c00
#define FPU_FS PSW_USB_C
#define FPU_FI PSW_USB_V
#define FPU_FV PSW_USB_SV
@@ -373,6 +375,45 @@ uint32_t helper_ftoi(CPUTriCoreState *env, uint32_t arg)
return (uint32_t)result;
}
+uint32_t helper_ftohp(CPUTriCoreState *env, uint32_t arg)
+{
+ float32 f_arg = make_float32(arg);
+ uint32_t result = 0;
+ int32_t flags = 0;
+
+ if (float32_is_infinity(f_arg)) {
+ if (float32_is_neg(f_arg)) {
+ return HP_NEG_INFINITY;
+ } else {
+ return HP_POS_INFINITY;
+ }
+ } else if (float32_is_any_nan(f_arg)) {
+ if (float32_is_signaling_nan(f_arg, &env->fp_status)) {
+ flags |= float_flag_invalid;
+ }
+ result = float16_set_sign(result, arg >> 31);
+ result = deposit32(result, 10, 5, 0x1f);
+ result = deposit32(result, 8, 2, extract32(arg, 21, 2));
+ result = deposit32(result, 0, 8, extract32(arg, 0, 8));
+ if (extract32(result, 0, 10) == 0) {
+ result |= (1 << 8);
+ }
+ } else {
+ set_flush_to_zero(0, &env->fp_status);
+ result = float32_to_float16(f_arg, true, &env->fp_status);
+ set_flush_to_zero(1, &env->fp_status);
+ flags = f_get_excp_flags(env);
+ }
+
+ if (flags) {
+ f_update_psw_flags(env, flags);
+ } else {
+ env->FPU_FS = 0;
+ }
+
+ return result;
+}
+
uint32_t helper_itof(CPUTriCoreState *env, uint32_t arg)
{
float32 f_result;
diff --git a/target/tricore/helper.c b/target/tricore/helper.c
index e615c3d6d4..6ccb52fea7 100644
--- a/target/tricore/helper.c
+++ b/target/tricore/helper.c
@@ -137,6 +137,7 @@ void fpu_set_state(CPUTriCoreState *env)
set_flush_inputs_to_zero(1, &env->fp_status);
set_flush_to_zero(1, &env->fp_status);
+ set_float_detect_tininess(true, &env->fp_status);
set_default_nan_mode(1, &env->fp_status);
}
diff --git a/target/tricore/helper.h b/target/tricore/helper.h
index 827fbaa692..dcc5a492b3 100644
--- a/target/tricore/helper.h
+++ b/target/tricore/helper.h
@@ -111,6 +111,7 @@ DEF_HELPER_4(fmsub, i32, env, i32, i32, i32)
DEF_HELPER_3(fcmp, i32, env, i32, i32)
DEF_HELPER_2(qseed, i32, env, i32)
DEF_HELPER_2(ftoi, i32, env, i32)
+DEF_HELPER_2(ftohp, i32, env, i32)
DEF_HELPER_2(itof, i32, env, i32)
DEF_HELPER_2(utof, i32, env, i32)
DEF_HELPER_2(ftoiz, i32, env, i32)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index fb9a7113a8..d94c273f89 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -6264,6 +6264,13 @@ static void decode_rr_divide(DisasContext *ctx)
case OPC2_32_RR_DIV_F:
gen_helper_fdiv(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
+ case OPC2_32_RR_FTOHP:
+ if (has_feature(ctx, TRICORE_FEATURE_162)) {
+ gen_helper_ftohp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+ } else {
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+ }
+ break;
case OPC2_32_RR_CMP_F:
gen_helper_fcmp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
diff --git a/target/tricore/tricore-opcodes.h b/target/tricore/tricore-opcodes.h
index f070571665..29e655a667 100644
--- a/target/tricore/tricore-opcodes.h
+++ b/target/tricore/tricore-opcodes.h
@@ -1152,6 +1152,7 @@ enum {
OPC2_32_RR_ITOF = 0x14,
OPC2_32_RR_CMP_F = 0x00,
OPC2_32_RR_FTOIZ = 0x13,
+ OPC2_32_RR_FTOHP = 0x25, /* 1.6.2 only */
OPC2_32_RR_FTOQ31 = 0x11,
OPC2_32_RR_FTOQ31Z = 0x18,
OPC2_32_RR_FTOU = 0x12,
diff --git a/tests/tcg/tricore/Makefile.softmmu-target b/tests/tcg/tricore/Makefile.softmmu-target
index e6ed5c56f2..f4a27a83e4 100644
--- a/tests/tcg/tricore/Makefile.softmmu-target
+++ b/tests/tcg/tricore/Makefile.softmmu-target
@@ -14,6 +14,7 @@ TESTS += test_dextr.asm.tst
TESTS += test_dvstep.asm.tst
TESTS += test_fadd.asm.tst
TESTS += test_fmul.asm.tst
+TESTS += test_ftohp.asm.tst
TESTS += test_ftoi.asm.tst
TESTS += test_ftou.asm.tst
TESTS += test_imask.asm.tst
diff --git a/tests/tcg/tricore/asm/test_ftohp.S b/tests/tcg/tricore/asm/test_ftohp.S
new file mode 100644
index 0000000000..9e23141c1e
--- /dev/null
+++ b/tests/tcg/tricore/asm/test_ftohp.S
@@ -0,0 +1,14 @@
+#include "macros.h"
+.text
+.global _start
+_start:
+ TEST_D_D(ftohp, 1, 0xffff, 0xffffffff)
+ TEST_D_D(ftohp, 2, 0xfc00, 0xff800000)
+ TEST_D_D(ftohp, 3, 0x7c00, 0x7f800000)
+ TEST_D_D(ftohp, 4, 0x0, 0x0)
+ TEST_D_D(ftohp, 5, 0x5, 0x34a43580)
+
+ #TEST_D_D_PSW(ftohp, 6, 0x400, 0x8c000b80, 0x387fee74)
+
+ TEST_PASSFAIL
+
--
2.41.0
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH 05/10] target/tricore: Implement ftohp insn
2023-08-26 16:02 ` [PATCH 05/10] target/tricore: Implement ftohp insn Bastian Koppelmann
@ 2023-08-27 4:55 ` Richard Henderson
2023-08-27 7:09 ` Bastian Koppelmann
0 siblings, 1 reply; 29+ messages in thread
From: Richard Henderson @ 2023-08-27 4:55 UTC (permalink / raw)
To: Bastian Koppelmann, qemu-devel; +Cc: anton.kochkov
On 8/26/23 09:02, Bastian Koppelmann wrote:
> +uint32_t helper_ftohp(CPUTriCoreState *env, uint32_t arg)
> +{
> + float32 f_arg = make_float32(arg);
> + uint32_t result = 0;
> + int32_t flags = 0;
> +
> + if (float32_is_infinity(f_arg)) {
> + if (float32_is_neg(f_arg)) {
> + return HP_NEG_INFINITY;
> + } else {
> + return HP_POS_INFINITY;
> + }
> + } else if (float32_is_any_nan(f_arg)) {
> + if (float32_is_signaling_nan(f_arg, &env->fp_status)) {
> + flags |= float_flag_invalid;
> + }
> + result = float16_set_sign(result, arg >> 31);
> + result = deposit32(result, 10, 5, 0x1f);
> + result = deposit32(result, 8, 2, extract32(arg, 21, 2));
> + result = deposit32(result, 0, 8, extract32(arg, 0, 8));
> + if (extract32(result, 0, 10) == 0) {
> + result |= (1 << 8);
> + }
> + } else {
> + set_flush_to_zero(0, &env->fp_status);
> + result = float32_to_float16(f_arg, true, &env->fp_status);
> + set_flush_to_zero(1, &env->fp_status);
> + flags = f_get_excp_flags(env);
> + }
All of this is standard behaviour. All you need is the final else case.
> + set_float_detect_tininess(true, &env->fp_status);
s/true/float_tininess_before_rounding/
r~
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH 05/10] target/tricore: Implement ftohp insn
2023-08-27 4:55 ` Richard Henderson
@ 2023-08-27 7:09 ` Bastian Koppelmann
2023-08-27 14:51 ` Richard Henderson
0 siblings, 1 reply; 29+ messages in thread
From: Bastian Koppelmann @ 2023-08-27 7:09 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, anton.kochkov
On Sat, Aug 26, 2023 at 09:55:05PM -0700, Richard Henderson wrote:
> On 8/26/23 09:02, Bastian Koppelmann wrote:
> > +uint32_t helper_ftohp(CPUTriCoreState *env, uint32_t arg)
> > +{
> > + float32 f_arg = make_float32(arg);
> > + uint32_t result = 0;
> > + int32_t flags = 0;
> > +
> > + if (float32_is_infinity(f_arg)) {
> > + if (float32_is_neg(f_arg)) {
> > + return HP_NEG_INFINITY;
> > + } else {
> > + return HP_POS_INFINITY;
> > + }
> > + } else if (float32_is_any_nan(f_arg)) {
> > + if (float32_is_signaling_nan(f_arg, &env->fp_status)) {
> > + flags |= float_flag_invalid;
> > + }
> > + result = float16_set_sign(result, arg >> 31);
> > + result = deposit32(result, 10, 5, 0x1f);
> > + result = deposit32(result, 8, 2, extract32(arg, 21, 2));
> > + result = deposit32(result, 0, 8, extract32(arg, 0, 8));
> > + if (extract32(result, 0, 10) == 0) {
> > + result |= (1 << 8);
> > + }
> > + } else {
> > + set_flush_to_zero(0, &env->fp_status);
> > + result = float32_to_float16(f_arg, true, &env->fp_status);
> > + set_flush_to_zero(1, &env->fp_status);
> > + flags = f_get_excp_flags(env);
> > + }
>
> All of this is standard behaviour. All you need is the final else case.
Unfortunately not quite. For NANs the top 2 and lower 8 output mantissa bits need to be
set to the top 2 and lower 8 input mantissa bits respectively. This behaviour is
unique to ftohp and hptof, so I don't think we should specialize it in
parts64_default_nan().
Cheers,
Bastian
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH 05/10] target/tricore: Implement ftohp insn
2023-08-27 7:09 ` Bastian Koppelmann
@ 2023-08-27 14:51 ` Richard Henderson
0 siblings, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2023-08-27 14:51 UTC (permalink / raw)
To: Bastian Koppelmann; +Cc: qemu-devel, anton.kochkov
On 8/27/23 00:09, Bastian Koppelmann wrote:
> On Sat, Aug 26, 2023 at 09:55:05PM -0700, Richard Henderson wrote:
>> On 8/26/23 09:02, Bastian Koppelmann wrote:
>>> +uint32_t helper_ftohp(CPUTriCoreState *env, uint32_t arg)
>>> +{
>>> + float32 f_arg = make_float32(arg);
>>> + uint32_t result = 0;
>>> + int32_t flags = 0;
>>> +
>>> + if (float32_is_infinity(f_arg)) {
>>> + if (float32_is_neg(f_arg)) {
>>> + return HP_NEG_INFINITY;
>>> + } else {
>>> + return HP_POS_INFINITY;
>>> + }
>>> + } else if (float32_is_any_nan(f_arg)) {
>>> + if (float32_is_signaling_nan(f_arg, &env->fp_status)) {
>>> + flags |= float_flag_invalid;
>>> + }
>>> + result = float16_set_sign(result, arg >> 31);
>>> + result = deposit32(result, 10, 5, 0x1f);
>>> + result = deposit32(result, 8, 2, extract32(arg, 21, 2));
>>> + result = deposit32(result, 0, 8, extract32(arg, 0, 8));
>>> + if (extract32(result, 0, 10) == 0) {
>>> + result |= (1 << 8);
>>> + }
>>> + } else {
>>> + set_flush_to_zero(0, &env->fp_status);
>>> + result = float32_to_float16(f_arg, true, &env->fp_status);
>>> + set_flush_to_zero(1, &env->fp_status);
>>> + flags = f_get_excp_flags(env);
>>> + }
>>
>> All of this is standard behaviour. All you need is the final else case.
>
> Unfortunately not quite. For NANs the top 2 and lower 8 output mantissa bits need to be
> set to the top 2 and lower 8 input mantissa bits respectively. This behaviour is
> unique to ftohp and hptof, so I don't think we should specialize it in
> parts64_default_nan().
Ah, whereas softfloat grabs the top 10 mantissa bits.
This could use a comment to that effect.
Certainly you don't need to special case infinity though.
r~
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 06/10] target/tricore: Implement hptof insn
2023-08-26 16:02 [PATCH 00/10] TriCore 1.6.2 insn and bugfixes Bastian Koppelmann
` (4 preceding siblings ...)
2023-08-26 16:02 ` [PATCH 05/10] target/tricore: Implement ftohp insn Bastian Koppelmann
@ 2023-08-26 16:02 ` Bastian Koppelmann
2023-08-27 4:56 ` Richard Henderson
2023-08-26 16:02 ` [PATCH 07/10] target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0 Bastian Koppelmann
` (3 subsequent siblings)
9 siblings, 1 reply; 29+ messages in thread
From: Bastian Koppelmann @ 2023-08-26 16:02 UTC (permalink / raw)
To: qemu-devel; +Cc: anton.kochkov, kbastian
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1667
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/fpu_helper.c | 39 +++++++++++++++++++++++
target/tricore/helper.h | 1 +
target/tricore/translate.c | 7 ++++
target/tricore/tricore-opcodes.h | 1 +
tests/tcg/tricore/Makefile.softmmu-target | 1 +
tests/tcg/tricore/asm/test_hptof.S | 12 +++++++
6 files changed, 61 insertions(+)
create mode 100644 tests/tcg/tricore/asm/test_hptof.S
diff --git a/target/tricore/fpu_helper.c b/target/tricore/fpu_helper.c
index 3db2341ac0..b91f872396 100644
--- a/target/tricore/fpu_helper.c
+++ b/target/tricore/fpu_helper.c
@@ -29,6 +29,8 @@
#define MUL_NAN 0x7fc00002
#define HP_NEG_INFINITY 0xfc00
#define HP_POS_INFINITY 0x7c00
+#define NEG_INFINITY 0xff800000
+#define POS_INFINITY 0x7f800000
#define FPU_FS PSW_USB_C
#define FPU_FI PSW_USB_V
#define FPU_FV PSW_USB_SV
@@ -375,6 +377,43 @@ uint32_t helper_ftoi(CPUTriCoreState *env, uint32_t arg)
return (uint32_t)result;
}
+uint32_t helper_hptof(CPUTriCoreState *env, uint32_t arg)
+{
+ float16 f_arg = make_float16(arg);
+ uint32_t result = 0;
+ int32_t flags = 0;
+
+ if (float16_is_any_nan(f_arg)) {
+ if (float16_is_signaling_nan(f_arg, &env->fp_status)) {
+ flags |= float_flag_invalid;
+ }
+ result = 0;
+ result = float32_set_sign(result, f_arg >> 15);
+ result = deposit32(result, 23, 8, 0xff);
+ result = deposit32(result, 21, 2, extract32(f_arg, 8, 2));
+ result = deposit32(result, 0, 8, extract32(f_arg, 0, 8));
+ } else if (float16_is_infinity(f_arg)) {
+ if (float16_is_neg(f_arg)) {
+ result = NEG_INFINITY;
+ } else {
+ result = POS_INFINITY;
+ }
+ } else {
+ set_flush_inputs_to_zero(0, &env->fp_status);
+ result = float16_to_float32(f_arg, true, &env->fp_status);
+ set_flush_inputs_to_zero(1, &env->fp_status);
+ flags = f_get_excp_flags(env);
+ }
+
+ if (flags) {
+ f_update_psw_flags(env, flags);
+ } else {
+ env->FPU_FS = 0;
+ }
+
+ return result;
+}
+
uint32_t helper_ftohp(CPUTriCoreState *env, uint32_t arg)
{
float32 f_arg = make_float32(arg);
diff --git a/target/tricore/helper.h b/target/tricore/helper.h
index dcc5a492b3..1d97d078b0 100644
--- a/target/tricore/helper.h
+++ b/target/tricore/helper.h
@@ -112,6 +112,7 @@ DEF_HELPER_3(fcmp, i32, env, i32, i32)
DEF_HELPER_2(qseed, i32, env, i32)
DEF_HELPER_2(ftoi, i32, env, i32)
DEF_HELPER_2(ftohp, i32, env, i32)
+DEF_HELPER_2(hptof, i32, env, i32)
DEF_HELPER_2(itof, i32, env, i32)
DEF_HELPER_2(utof, i32, env, i32)
DEF_HELPER_2(ftoiz, i32, env, i32)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index d94c273f89..4400d2c3cb 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -6271,6 +6271,13 @@ static void decode_rr_divide(DisasContext *ctx)
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
+ case OPC2_32_RR_HPTOF:
+ if (has_feature(ctx, TRICORE_FEATURE_162)) {
+ gen_helper_hptof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+ } else {
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+ }
+ break;
case OPC2_32_RR_CMP_F:
gen_helper_fcmp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
diff --git a/target/tricore/tricore-opcodes.h b/target/tricore/tricore-opcodes.h
index 29e655a667..60d2402b6e 100644
--- a/target/tricore/tricore-opcodes.h
+++ b/target/tricore/tricore-opcodes.h
@@ -1153,6 +1153,7 @@ enum {
OPC2_32_RR_CMP_F = 0x00,
OPC2_32_RR_FTOIZ = 0x13,
OPC2_32_RR_FTOHP = 0x25, /* 1.6.2 only */
+ OPC2_32_RR_HPTOF = 0x24, /* 1.6.2 only */
OPC2_32_RR_FTOQ31 = 0x11,
OPC2_32_RR_FTOQ31Z = 0x18,
OPC2_32_RR_FTOU = 0x12,
diff --git a/tests/tcg/tricore/Makefile.softmmu-target b/tests/tcg/tricore/Makefile.softmmu-target
index f4a27a83e4..afcf41a977 100644
--- a/tests/tcg/tricore/Makefile.softmmu-target
+++ b/tests/tcg/tricore/Makefile.softmmu-target
@@ -17,6 +17,7 @@ TESTS += test_fmul.asm.tst
TESTS += test_ftohp.asm.tst
TESTS += test_ftoi.asm.tst
TESTS += test_ftou.asm.tst
+TESTS += test_hptof.asm.tst
TESTS += test_imask.asm.tst
TESTS += test_insert.asm.tst
TESTS += test_ld_bu.asm.tst
diff --git a/tests/tcg/tricore/asm/test_hptof.S b/tests/tcg/tricore/asm/test_hptof.S
new file mode 100644
index 0000000000..8adc5e5273
--- /dev/null
+++ b/tests/tcg/tricore/asm/test_hptof.S
@@ -0,0 +1,12 @@
+#include "macros.h"
+.text
+.global _start
+_start:
+ TEST_D_D(hptof, 1, 0xba190000, 0xcc0e90c8)
+ TEST_D_D(hptof, 2, 0x3eaea000, 0x8be23575)
+ TEST_D_D(hptof, 3, 0xc33b8000, 0xcc48d9dc)
+ TEST_D_D(hptof, 4, 0x43e2a000, 0xaef95f15)
+ TEST_D_D(hptof, 5, 0x3d55e000, 0x04932aaf)
+
+ TEST_PASSFAIL
+
--
2.41.0
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH 06/10] target/tricore: Implement hptof insn
2023-08-26 16:02 ` [PATCH 06/10] target/tricore: Implement hptof insn Bastian Koppelmann
@ 2023-08-27 4:56 ` Richard Henderson
0 siblings, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2023-08-27 4:56 UTC (permalink / raw)
To: Bastian Koppelmann, qemu-devel; +Cc: anton.kochkov
On 8/26/23 09:02, Bastian Koppelmann wrote:
> +uint32_t helper_hptof(CPUTriCoreState *env, uint32_t arg)
> +{
> + float16 f_arg = make_float16(arg);
> + uint32_t result = 0;
> + int32_t flags = 0;
> +
> + if (float16_is_any_nan(f_arg)) {
> + if (float16_is_signaling_nan(f_arg, &env->fp_status)) {
> + flags |= float_flag_invalid;
> + }
> + result = 0;
> + result = float32_set_sign(result, f_arg >> 15);
> + result = deposit32(result, 23, 8, 0xff);
> + result = deposit32(result, 21, 2, extract32(f_arg, 8, 2));
> + result = deposit32(result, 0, 8, extract32(f_arg, 0, 8));
> + } else if (float16_is_infinity(f_arg)) {
> + if (float16_is_neg(f_arg)) {
> + result = NEG_INFINITY;
> + } else {
> + result = POS_INFINITY;
> + }
> + } else {
> + set_flush_inputs_to_zero(0, &env->fp_status);
> + result = float16_to_float32(f_arg, true, &env->fp_status);
> + set_flush_inputs_to_zero(1, &env->fp_status);
> + flags = f_get_excp_flags(env);
> + }
Again, only the else case.
r~
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 07/10] target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0
2023-08-26 16:02 [PATCH 00/10] TriCore 1.6.2 insn and bugfixes Bastian Koppelmann
` (5 preceding siblings ...)
2023-08-26 16:02 ` [PATCH 06/10] target/tricore: Implement hptof insn Bastian Koppelmann
@ 2023-08-26 16:02 ` Bastian Koppelmann
2023-08-27 4:59 ` Richard Henderson
2023-08-26 16:02 ` [PATCH 08/10] target/tricore: Swap src and dst reg for RCRR_INSERT Bastian Koppelmann
` (2 subsequent siblings)
9 siblings, 1 reply; 29+ messages in thread
From: Bastian Koppelmann @ 2023-08-26 16:02 UTC (permalink / raw)
To: qemu-devel; +Cc: anton.kochkov, kbastian
we would crash if width was 0 for these insns, as tcg_gen_deposit() is
undefined for that case. For TriCore, width = 0 is a mov from the src reg
to the dst reg, so we special case this here.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/translate.c | 10 ++++++++--
tests/tcg/tricore/asm/macros.h | 15 +++++++++++++++
tests/tcg/tricore/asm/test_insert.S | 9 +++++++++
3 files changed, 32 insertions(+), 2 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 4400d2c3cb..d13f85c03a 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -5317,8 +5317,11 @@ static void decode_rcpw_insert(DisasContext *ctx)
}
break;
case OPC2_32_RCPW_INSERT:
+ /* tcg_gen_deposit_tl() does not handle the case of width = 0 */
+ if (width == 0) {
+ tcg_gen_mov_tl(cpu_gpr_d[r2], cpu_gpr_d[r1]);
/* if pos + width > 32 undefined result */
- if (pos + width <= 32) {
+ } else if (pos + width <= 32) {
temp = tcg_constant_i32(const4);
tcg_gen_deposit_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, width);
}
@@ -6575,7 +6578,10 @@ static void decode_rrpw_extract_insert(DisasContext *ctx)
break;
case OPC2_32_RRPW_INSERT:
- if (pos + width <= 32) {
+ /* tcg_gen_deposit_tl() does not handle the case of width = 0 */
+ if (width == 0) {
+ tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
+ } else if (pos + width <= 32) {
tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
pos, width);
}
diff --git a/tests/tcg/tricore/asm/macros.h b/tests/tcg/tricore/asm/macros.h
index b5087b5c97..51f6191ef2 100644
--- a/tests/tcg/tricore/asm/macros.h
+++ b/tests/tcg/tricore/asm/macros.h
@@ -161,6 +161,21 @@ test_ ## num: \
insn DREG_CALC_RESULT, DREG_RS1, imm1, DREG_RS2, imm2; \
)
+#define TEST_D_DDII(insn, num, result, rs1, rs2, imm1, imm2) \
+ TEST_CASE(num, DREG_CALC_RESULT, result, \
+ LI(DREG_RS1, rs1); \
+ LI(DREG_RS2, rs2); \
+ rstv; \
+ insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, imm1, imm2; \
+ )
+
+#define TEST_D_DIII(insn, num, result, rs1, imm1, imm2, imm3)\
+ TEST_CASE(num, DREG_CALC_RESULT, result, \
+ LI(DREG_RS1, rs1); \
+ rstv; \
+ insn DREG_CALC_RESULT, DREG_RS1, imm1, imm2, imm3; \
+ )
+
#define TEST_E_ED(insn, num, res_hi, res_lo, rs1_hi, rs1_lo, rs2) \
TEST_CASE_E(num, res_lo, res_hi, \
LI(EREG_RS1_LO, rs1_lo); \
diff --git a/tests/tcg/tricore/asm/test_insert.S b/tests/tcg/tricore/asm/test_insert.S
index d5fd2237e1..3978810121 100644
--- a/tests/tcg/tricore/asm/test_insert.S
+++ b/tests/tcg/tricore/asm/test_insert.S
@@ -6,4 +6,13 @@ _start:
# | | | | | | |
TEST_D_DIDI(insert, 1, 0x7fffffff, 0xffffffff, 0xa, 0x10, 0x8)
+# insn num result rs1 imm1 imm2 imm3
+# | | | | | | |
+ TEST_D_DIII(insert, 2, 0xd38fe370, 0xd38fe370, 0x4, 0x4 , 0x0)
+ TEST_D_DIII(insert, 3, 0xd38fe374, 0xd38fe370, 0x4, 0x0 , 0x4)
+
+# insn num result rs1 rs2 pos width
+# | | | | | | |
+ TEST_D_DDII(insert, 4, 0x03c1e53c, 0x03c1e53c, 0x45821385, 0x7 ,0x0)
+
TEST_PASSFAIL
--
2.41.0
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH 07/10] target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0
2023-08-26 16:02 ` [PATCH 07/10] target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0 Bastian Koppelmann
@ 2023-08-27 4:59 ` Richard Henderson
0 siblings, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2023-08-27 4:59 UTC (permalink / raw)
To: Bastian Koppelmann, qemu-devel; +Cc: anton.kochkov
On 8/26/23 09:02, Bastian Koppelmann wrote:
> we would crash if width was 0 for these insns, as tcg_gen_deposit() is
> undefined for that case. For TriCore, width = 0 is a mov from the src reg
> to the dst reg, so we special case this here.
>
> Signed-off-by: Bastian Koppelmann<kbastian@mail.uni-paderborn.de>
> ---
> target/tricore/translate.c | 10 ++++++++--
> tests/tcg/tricore/asm/macros.h | 15 +++++++++++++++
> tests/tcg/tricore/asm/test_insert.S | 9 +++++++++
> 3 files changed, 32 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 08/10] target/tricore: Swap src and dst reg for RCRR_INSERT
2023-08-26 16:02 [PATCH 00/10] TriCore 1.6.2 insn and bugfixes Bastian Koppelmann
` (6 preceding siblings ...)
2023-08-26 16:02 ` [PATCH 07/10] target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0 Bastian Koppelmann
@ 2023-08-26 16:02 ` Bastian Koppelmann
2023-08-27 5:06 ` Richard Henderson
2023-08-26 16:02 ` [PATCH 09/10] target/tricore: Replace cpu_*_code with translator_* Bastian Koppelmann
2023-08-26 16:02 ` [PATCH 10/10] target/tricore: Fix FTOUZ being ISA v1.3.1 up Bastian Koppelmann
9 siblings, 1 reply; 29+ messages in thread
From: Bastian Koppelmann @ 2023-08-26 16:02 UTC (permalink / raw)
To: qemu-devel; +Cc: anton.kochkov, kbastian
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/translate.c | 8 ++++----
tests/tcg/tricore/asm/macros.h | 9 +++++++++
tests/tcg/tricore/asm/test_insert.S | 5 +++++
3 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index d13f85c03a..a68660b326 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -8225,12 +8225,12 @@ static void decode_32Bit_opc(DisasContext *ctx)
temp2 = tcg_temp_new(); /* width*/
temp3 = tcg_temp_new(); /* pos */
- CHECK_REG_PAIR(r3);
+ CHECK_REG_PAIR(r2);
- tcg_gen_andi_tl(temp2, cpu_gpr_d[r3+1], 0x1f);
- tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f);
+ tcg_gen_andi_tl(temp2, cpu_gpr_d[r2 + 1], 0x1f);
+ tcg_gen_andi_tl(temp3, cpu_gpr_d[r2], 0x1f);
- gen_insert(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, temp2, temp3);
+ gen_insert(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, temp2, temp3);
break;
/* RCRW Format */
case OPCM_32_RCRW_MASK_INSERT:
diff --git a/tests/tcg/tricore/asm/macros.h b/tests/tcg/tricore/asm/macros.h
index 51f6191ef2..17e696bef5 100644
--- a/tests/tcg/tricore/asm/macros.h
+++ b/tests/tcg/tricore/asm/macros.h
@@ -169,6 +169,15 @@ test_ ## num: \
insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, imm1, imm2; \
)
+#define TEST_D_DIE(insn, num, result, rs1, imm1, rs2_lo, rs2_hi)\
+ TEST_CASE(num, DREG_CALC_RESULT, result, \
+ LI(DREG_RS1, rs1); \
+ LI(EREG_RS2_LO, rs2_lo); \
+ LI(EREG_RS2_HI, rs2_hi); \
+ rstv; \
+ insn DREG_CALC_RESULT, DREG_RS1, imm1, EREG_RS2; \
+ )
+
#define TEST_D_DIII(insn, num, result, rs1, imm1, imm2, imm3)\
TEST_CASE(num, DREG_CALC_RESULT, result, \
LI(DREG_RS1, rs1); \
diff --git a/tests/tcg/tricore/asm/test_insert.S b/tests/tcg/tricore/asm/test_insert.S
index 3978810121..223d7ce796 100644
--- a/tests/tcg/tricore/asm/test_insert.S
+++ b/tests/tcg/tricore/asm/test_insert.S
@@ -15,4 +15,9 @@ _start:
# | | | | | | |
TEST_D_DDII(insert, 4, 0x03c1e53c, 0x03c1e53c, 0x45821385, 0x7 ,0x0)
+# insn num result rs1 imm1 rs2_h rs2_l
+# | | | | | | |
+ TEST_D_DIE(insert, 5, 0xe30c308d, 0xe30c308d ,0x3 , 0x00000000 ,0x00000000)
+ TEST_D_DIE(insert, 6, 0x669b0120, 0x669b2820 ,0x2 , 0x5530a1c7 ,0x3a2b0f67)
+
TEST_PASSFAIL
--
2.41.0
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH 08/10] target/tricore: Swap src and dst reg for RCRR_INSERT
2023-08-26 16:02 ` [PATCH 08/10] target/tricore: Swap src and dst reg for RCRR_INSERT Bastian Koppelmann
@ 2023-08-27 5:06 ` Richard Henderson
2023-08-27 7:18 ` Bastian Koppelmann
0 siblings, 1 reply; 29+ messages in thread
From: Richard Henderson @ 2023-08-27 5:06 UTC (permalink / raw)
To: Bastian Koppelmann, qemu-devel; +Cc: anton.kochkov
On 8/26/23 09:02, Bastian Koppelmann wrote:
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> ---
> target/tricore/translate.c | 8 ++++----
> tests/tcg/tricore/asm/macros.h | 9 +++++++++
> tests/tcg/tricore/asm/test_insert.S | 5 +++++
> 3 files changed, 18 insertions(+), 4 deletions(-)
>
> diff --git a/target/tricore/translate.c b/target/tricore/translate.c
> index d13f85c03a..a68660b326 100644
> --- a/target/tricore/translate.c
> +++ b/target/tricore/translate.c
> @@ -8225,12 +8225,12 @@ static void decode_32Bit_opc(DisasContext *ctx)
> temp2 = tcg_temp_new(); /* width*/
> temp3 = tcg_temp_new(); /* pos */
>
> - CHECK_REG_PAIR(r3);
> + CHECK_REG_PAIR(r2);
While it looks as if the end result is the same, it appears the macros used just above are
wrong. The field definitions for RCRR on page 1-4 do not match the field definitions for
INSERT.RCRR on page 3-118.
r~
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 08/10] target/tricore: Swap src and dst reg for RCRR_INSERT
2023-08-27 5:06 ` Richard Henderson
@ 2023-08-27 7:18 ` Bastian Koppelmann
0 siblings, 0 replies; 29+ messages in thread
From: Bastian Koppelmann @ 2023-08-27 7:18 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, anton.kochkov
On Sat, Aug 26, 2023 at 10:06:22PM -0700, Richard Henderson wrote:
> On 8/26/23 09:02, Bastian Koppelmann wrote:
> > Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> > ---
> > target/tricore/translate.c | 8 ++++----
> > tests/tcg/tricore/asm/macros.h | 9 +++++++++
> > tests/tcg/tricore/asm/test_insert.S | 5 +++++
> > 3 files changed, 18 insertions(+), 4 deletions(-)
> >
> > diff --git a/target/tricore/translate.c b/target/tricore/translate.c
> > index d13f85c03a..a68660b326 100644
> > --- a/target/tricore/translate.c
> > +++ b/target/tricore/translate.c
> > @@ -8225,12 +8225,12 @@ static void decode_32Bit_opc(DisasContext *ctx)
> > temp2 = tcg_temp_new(); /* width*/
> > temp3 = tcg_temp_new(); /* pos */
> > - CHECK_REG_PAIR(r3);
> > + CHECK_REG_PAIR(r2);
>
> While it looks as if the end result is the same, it appears the macros used
> just above are wrong. The field definitions for RCRR on page 1-4 do not
> match the field definitions for INSERT.RCRR on page 3-118.
Looks correct to me. I guess it is confusing that RCRR on page 1-4 uses s1, s2,
etc., and d for the reg names, while INSERT.RCRR on page 3-118 enumerates the reg
names from a to d. So the "d" for dst from page 1-4 is not the same "d" on page
3-118.
Cheers,
Bastian
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 09/10] target/tricore: Replace cpu_*_code with translator_*
2023-08-26 16:02 [PATCH 00/10] TriCore 1.6.2 insn and bugfixes Bastian Koppelmann
` (7 preceding siblings ...)
2023-08-26 16:02 ` [PATCH 08/10] target/tricore: Swap src and dst reg for RCRR_INSERT Bastian Koppelmann
@ 2023-08-26 16:02 ` Bastian Koppelmann
2023-08-27 5:06 ` Richard Henderson
2023-08-26 16:02 ` [PATCH 10/10] target/tricore: Fix FTOUZ being ISA v1.3.1 up Bastian Koppelmann
9 siblings, 1 reply; 29+ messages in thread
From: Bastian Koppelmann @ 2023-08-26 16:02 UTC (permalink / raw)
To: qemu-devel; +Cc: anton.kochkov, kbastian
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/translate.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index a68660b326..89ed48c951 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -8400,7 +8400,7 @@ static bool insn_crosses_page(CPUTriCoreState *env, DisasContext *ctx)
* 4 bytes from the page boundary, so we cross the page if the first
* 16 bits indicate that this is a 32 bit insn.
*/
- uint16_t insn = cpu_lduw_code(env, ctx->base.pc_next);
+ uint16_t insn = translator_lduw(env, &ctx->base, ctx->base.pc_next);
return !tricore_insn_is_16bit(insn);
}
@@ -8413,14 +8413,15 @@ static void tricore_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
uint16_t insn_lo;
bool is_16bit;
- insn_lo = cpu_lduw_code(env, ctx->base.pc_next);
+ insn_lo = translator_lduw(env, &ctx->base, ctx->base.pc_next);
is_16bit = tricore_insn_is_16bit(insn_lo);
if (is_16bit) {
ctx->opcode = insn_lo;
ctx->pc_succ_insn = ctx->base.pc_next + 2;
decode_16Bit_opc(ctx);
} else {
- uint32_t insn_hi = cpu_lduw_code(env, ctx->base.pc_next + 2);
+ uint32_t insn_hi = translator_lduw(env, &ctx->base,
+ ctx->base.pc_next + 2);
ctx->opcode = insn_hi << 16 | insn_lo;
ctx->pc_succ_insn = ctx->base.pc_next + 4;
decode_32Bit_opc(ctx);
--
2.41.0
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 10/10] target/tricore: Fix FTOUZ being ISA v1.3.1 up
2023-08-26 16:02 [PATCH 00/10] TriCore 1.6.2 insn and bugfixes Bastian Koppelmann
` (8 preceding siblings ...)
2023-08-26 16:02 ` [PATCH 09/10] target/tricore: Replace cpu_*_code with translator_* Bastian Koppelmann
@ 2023-08-26 16:02 ` Bastian Koppelmann
2023-08-27 5:06 ` Richard Henderson
9 siblings, 1 reply; 29+ messages in thread
From: Bastian Koppelmann @ 2023-08-26 16:02 UTC (permalink / raw)
To: qemu-devel; +Cc: anton.kochkov, kbastian
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/translate.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 89ed48c951..a7865db75c 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -6294,7 +6294,11 @@ static void decode_rr_divide(DisasContext *ctx)
gen_helper_ftou(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
break;
case OPC2_32_RR_FTOUZ:
- gen_helper_ftouz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+ if (has_feature(ctx, TRICORE_FEATURE_131)) {
+ gen_helper_ftouz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+ } else {
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+ }
break;
case OPC2_32_RR_UPDFL:
gen_helper_updfl(cpu_env, cpu_gpr_d[r1]);
--
2.41.0
^ permalink raw reply related [flat|nested] 29+ messages in thread