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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45b7e8ab093sm157419385e9.22.2025.09.01.04.09.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 01 Sep 2025 04:09:04 -0700 (PDT) Message-ID: Date: Mon, 1 Sep 2025 13:09:03 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 07/14] target/riscv: Add Xmipslsp instructions To: Djordje Todorovic , "qemu-devel@nongnu.org" Cc: "qemu-riscv@nongnu.org" , "cfu@mips.com" , "mst@redhat.com" , "marcel.apfelbaum@gmail.com" , "dbarboza@ventanamicro.com" References: <20250717093833.402237-1-djordje.todorovic@htecgroup.com> <20250717093833.402237-8-djordje.todorovic@htecgroup.com> <87427d18-af1e-4815-b95f-75bae32720d3@linaro.org> <00c8547e-dbbc-44d3-bcdf-122899d7dc2e@htecgroup.com> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <00c8547e-dbbc-44d3-bcdf-122899d7dc2e@htecgroup.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 1/9/25 10:30, Djordje Todorovic wrote: > > On 8. 8. 25. 18:02, Philippe Mathieu-Daudé wrote: >> CAUTION: This email originated from outside of the organization. Do >> not click links or open attachments unless you recognize the sender >> and know the content is safe. >> >> >> On 17/7/25 11:38, Djordje Todorovic wrote: >>> Add MIPS P8700 ldp, lwp, sdp, swp instructions. >>> >>> Signed-off-by: Chao-ying Fu >>> Signed-off-by: Djordje Todorovic >>> --- >>>   target/riscv/cpu.c                        |  3 + >>>   target/riscv/cpu_cfg.h                    |  2 +- >>>   target/riscv/cpu_cfg_fields.h.inc         |  1 + >>>   target/riscv/insn_trans/trans_xmips.c.inc | 84 +++++++++++++++++++++++ >>>   target/riscv/xmips.decode                 | 23 +++++++ >>>   5 files changed, 112 insertions(+), 1 deletion(-) >> >> >>> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h >>> index 9734963035..f35d477f27 100644 >>> --- a/target/riscv/cpu_cfg.h >>> +++ b/target/riscv/cpu_cfg.h >>> @@ -39,7 +39,7 @@ static inline bool always_true_p(const >>> RISCVCPUConfig *cfg __attribute__((__unus >>> >>>   static inline bool has_xmips_p(const RISCVCPUConfig *cfg) >>>   { >>> -    return cfg->ext_xmipscbop || cfg->ext_xmipscmov; >>> +    return cfg->ext_xmipscbop || cfg->ext_xmipscmov || >>> cfg->ext_xmipslsp; >> >> Checking for any XMIPS instruction implemented to return vendor >> extension presence seems odd. Can you implement them separately? > > And I tried several options, but it only made the code even "more off" :( OK, maybe this is the correct way to go then.