From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Subject: Re: [PATCH 21/23] accel/tcg: Remove CPUTLBDesc.fulltlb
Date: Wed, 9 Oct 2024 17:38:46 -0700 [thread overview]
Message-ID: <f95b79b3-e1b1-4d24-9c78-b4c6c28c1695@linaro.org> (raw)
In-Reply-To: <20241009150855.804605-22-richard.henderson@linaro.org>
On 10/9/24 08:08, Richard Henderson wrote:
> This array is now write-only, and may be remove.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/hw/core/cpu.h | 1 -
> accel/tcg/cputlb.c | 39 ++++++++-------------------------------
> 2 files changed, 8 insertions(+), 32 deletions(-)
>
> diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
> index 6b1c2bfadd..3022529733 100644
> --- a/include/hw/core/cpu.h
> +++ b/include/hw/core/cpu.h
> @@ -216,7 +216,6 @@ typedef struct CPUTLBDesc {
> /* maximum number of entries observed in the window */
> size_t window_max_entries;
> size_t n_used_entries;
> - CPUTLBEntryFull *fulltlb;
> /* All active tlb entries for this address space. */
> IntervalTreeRoot iroot;
> } CPUTLBDesc;
> diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
> index 2a8d1b4fb2..47b9557bb8 100644
> --- a/accel/tcg/cputlb.c
> +++ b/accel/tcg/cputlb.c
> @@ -149,13 +149,6 @@ static inline CPUTLBEntry *tlbfast_entry(CPUTLBDescFast *fast, vaddr addr)
> return fast->table + tlbfast_index(fast, addr);
> }
>
> -/* Find the TLB index corresponding to the mmu_idx + address pair. */
> -static inline uintptr_t tlb_index(CPUState *cpu, uintptr_t mmu_idx,
> - vaddr addr)
> -{
> - return tlbfast_index(&cpu->neg.tlb.f[mmu_idx], addr);
> -}
> -
> /* Find the TLB entry corresponding to the mmu_idx + address pair. */
> static inline CPUTLBEntry *tlb_entry(CPUState *cpu, uintptr_t mmu_idx,
> vaddr addr)
> @@ -270,22 +263,20 @@ static void tlb_mmu_resize_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast,
> }
>
> g_free(fast->table);
> - g_free(desc->fulltlb);
>
> tlb_window_reset(desc, now, 0);
> /* desc->n_used_entries is cleared by the caller */
> fast->mask = (new_size - 1) << CPU_TLB_ENTRY_BITS;
> fast->table = g_try_new(CPUTLBEntry, new_size);
> - desc->fulltlb = g_try_new(CPUTLBEntryFull, new_size);
>
> /*
> - * If the allocations fail, try smaller sizes. We just freed some
> + * If the allocation fails, try smaller sizes. We just freed some
> * memory, so going back to half of new_size has a good chance of working.
> * Increased memory pressure elsewhere in the system might cause the
> * allocations to fail though, so we progressively reduce the allocation
> * size, aborting if we cannot even allocate the smallest TLB we support.
> */
> - while (fast->table == NULL || desc->fulltlb == NULL) {
> + while (fast->table == NULL) {
> if (new_size == (1 << CPU_TLB_DYN_MIN_BITS)) {
> error_report("%s: %s", __func__, strerror(errno));
> abort();
> @@ -294,9 +285,7 @@ static void tlb_mmu_resize_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast,
> fast->mask = (new_size - 1) << CPU_TLB_ENTRY_BITS;
>
> g_free(fast->table);
> - g_free(desc->fulltlb);
> fast->table = g_try_new(CPUTLBEntry, new_size);
> - desc->fulltlb = g_try_new(CPUTLBEntryFull, new_size);
> }
> }
>
> @@ -350,7 +339,6 @@ static void tlb_mmu_init(CPUTLBDesc *desc, CPUTLBDescFast *fast, int64_t now)
> desc->n_used_entries = 0;
> fast->mask = (n_entries - 1) << CPU_TLB_ENTRY_BITS;
> fast->table = g_new(CPUTLBEntry, n_entries);
> - desc->fulltlb = g_new(CPUTLBEntryFull, n_entries);
> memset(&desc->iroot, 0, sizeof(desc->iroot));
> tlb_mmu_flush_locked(desc, fast);
> }
> @@ -382,15 +370,9 @@ void tlb_init(CPUState *cpu)
>
> void tlb_destroy(CPUState *cpu)
> {
> - int i;
> -
> qemu_spin_destroy(&cpu->neg.tlb.c.lock);
> - for (i = 0; i < NB_MMU_MODES; i++) {
> - CPUTLBDesc *desc = &cpu->neg.tlb.d[i];
> - CPUTLBDescFast *fast = &cpu->neg.tlb.f[i];
> -
> - g_free(fast->table);
> - g_free(desc->fulltlb);
> + for (int i = 0; i < NB_MMU_MODES; i++) {
> + g_free(cpu->neg.tlb.f[i].table);
> interval_tree_free_nodes(&cpu->neg.tlb.d[i].iroot,
> offsetof(CPUTLBEntryTree, itree));
> }
> @@ -1090,7 +1072,7 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx,
> CPUTLB *tlb = &cpu->neg.tlb;
> CPUTLBDesc *desc = &tlb->d[mmu_idx];
> MemoryRegionSection *section;
> - unsigned int index, read_flags, write_flags;
> + unsigned int read_flags, write_flags;
> uintptr_t addend;
> CPUTLBEntry *te;
> CPUTLBEntryTree *node;
> @@ -1169,7 +1151,6 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx,
> wp_flags = cpu_watchpoint_address_matches(cpu, addr_page,
> TARGET_PAGE_SIZE);
>
> - index = tlb_index(cpu, mmu_idx, addr_page);
> te = tlb_entry(cpu, mmu_idx, addr_page);
>
> /*
> @@ -1208,8 +1189,8 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx,
> * subtract here is that of the page base, and not the same as the
> * vaddr we add back in io_prepare()/get_page_addr_code().
> */
> - desc->fulltlb[index] = *full;
> - full = &desc->fulltlb[index];
> + node->full = *full;
> + full = &node->full;
> full->xlat_section = iotlb - addr_page;
> full->phys_addr = paddr_page;
>
> @@ -1232,7 +1213,6 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx,
> tlb_set_compare(full, &node->copy, addr_page, write_flags,
> MMU_DATA_STORE, prot & PAGE_WRITE);
>
> - node->full = *full;
> copy_tlb_helper_locked(te, &node->copy);
> tlb_n_used_entries_inc(cpu, mmu_idx);
> qemu_spin_unlock(&tlb->c.lock);
> @@ -1343,7 +1323,6 @@ static bool tlbtree_hit(CPUState *cpu, int mmu_idx,
> CPUTLBDesc *desc = &cpu->neg.tlb.d[mmu_idx];
> CPUTLBDescFast *fast = &cpu->neg.tlb.f[mmu_idx];
> CPUTLBEntryTree *node;
> - size_t index;
>
> assert_cpu_is_self(cpu);
> node = tlbtree_lookup_addr(desc, addr);
> @@ -1358,12 +1337,10 @@ static bool tlbtree_hit(CPUState *cpu, int mmu_idx,
> }
>
> /* Install the cached entry. */
> - index = tlbfast_index(fast, addr);
> qemu_spin_lock(&cpu->neg.tlb.c.lock);
> - copy_tlb_helper_locked(&fast->table[index], &node->copy);
> + copy_tlb_helper_locked(tlbfast_entry(fast, addr), &node->copy);
> qemu_spin_unlock(&cpu->neg.tlb.c.lock);
>
> - desc->fulltlb[index] = node->full;
> return true;
> }
>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
next prev parent reply other threads:[~2024-10-10 0:39 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-09 15:08 [RFC PATCH 00/23] accel/tcg: Convert victim tlb to IntervalTree Richard Henderson
2024-10-09 15:08 ` [PATCH 01/23] util/interval-tree: Introduce interval_tree_free_nodes Richard Henderson
2024-10-09 22:51 ` Pierrick Bouvier
2024-10-09 15:08 ` [PATCH 02/23] accel/tcg: Split out tlbfast_flush_locked Richard Henderson
2024-10-09 18:54 ` Philippe Mathieu-Daudé
2024-10-09 22:53 ` Pierrick Bouvier
2024-10-09 15:08 ` [PATCH 03/23] accel/tcg: Split out tlbfast_{index,entry} Richard Henderson
2024-10-09 22:55 ` Pierrick Bouvier
2024-10-09 15:08 ` [PATCH 04/23] accel/tcg: Split out tlbfast_flush_range_locked Richard Henderson
2024-10-09 23:05 ` Pierrick Bouvier
2024-10-10 1:20 ` Richard Henderson
2024-10-11 17:09 ` Pierrick Bouvier
2024-10-09 15:08 ` [PATCH 05/23] accel/tcg: Fix flags usage in mmu_lookup1, atomic_mmu_lookup Richard Henderson
2024-10-09 23:18 ` Pierrick Bouvier
2024-10-09 15:08 ` [PATCH 06/23] accel/tcg: Early exit for zero length in tlb_flush_range_by_mmuidx* Richard Henderson
2024-10-09 18:53 ` Philippe Mathieu-Daudé
2024-10-09 23:20 ` Pierrick Bouvier
2024-10-09 15:08 ` [PATCH 07/23] accel/tcg: Flush entire tlb when a masked range wraps Richard Henderson
2024-10-09 23:28 ` Pierrick Bouvier
2024-10-09 15:08 ` [PATCH 08/23] accel/tcg: Add IntervalTreeRoot to CPUTLBDesc Richard Henderson
2024-10-09 23:31 ` Pierrick Bouvier
2024-10-09 15:08 ` [PATCH 09/23] accel/tcg: Populate IntervalTree in tlb_set_page_full Richard Henderson
2024-10-09 23:50 ` Pierrick Bouvier
2024-10-09 15:08 ` [PATCH 10/23] accel/tcg: Remove IntervalTree entry in tlb_flush_page_locked Richard Henderson
2024-10-09 23:53 ` Pierrick Bouvier
2024-10-09 15:08 ` [PATCH 11/23] accel/tcg: Remove IntervalTree entries in tlb_flush_range_locked Richard Henderson
2024-10-09 23:57 ` Pierrick Bouvier
2024-10-09 15:08 ` [PATCH 12/23] accel/tcg: Process IntervalTree entries in tlb_reset_dirty Richard Henderson
2024-10-10 0:03 ` Pierrick Bouvier
2024-10-09 15:08 ` [PATCH 13/23] accel/tcg: Process IntervalTree entries in tlb_set_dirty Richard Henderson
2024-10-10 0:04 ` Pierrick Bouvier
2024-10-09 15:08 ` [PATCH 14/23] accel/tcg: Replace victim_tlb_hit with tlbtree_hit Richard Henderson
2024-10-10 0:10 ` Pierrick Bouvier
2024-10-10 19:29 ` Richard Henderson
2024-10-11 17:11 ` Pierrick Bouvier
2024-10-09 15:08 ` [PATCH 15/23] accel/tcg: Remove the victim tlb Richard Henderson
2024-10-10 0:12 ` Pierrick Bouvier
2024-10-09 15:08 ` [PATCH 16/23] include/exec/tlb-common: Move CPUTLBEntryFull from hw/core/cpu.h Richard Henderson
2024-10-10 0:17 ` Pierrick Bouvier
2024-10-09 15:08 ` [PATCH 17/23] accel/tcg: Delay plugin adjustment in probe_access_internal Richard Henderson
2024-10-10 0:19 ` Pierrick Bouvier
2024-10-09 15:08 ` [PATCH 18/23] accel/tcg: Call cpu_ld*_code_mmu from cpu_ld*_code Richard Henderson
2024-10-09 18:51 ` Philippe Mathieu-Daudé
2024-10-10 0:23 ` Pierrick Bouvier
2024-10-10 19:31 ` Richard Henderson
2024-10-09 15:08 ` [PATCH 19/23] accel/tcg: Always use IntervalTree for code lookups Richard Henderson
2024-10-10 0:35 ` Pierrick Bouvier
2024-10-11 14:47 ` Richard Henderson
2024-10-11 17:55 ` Pierrick Bouvier
2024-10-09 15:08 ` [PATCH 20/23] accel/tcg: Link CPUTLBEntry to CPUTLBEntryTree Richard Henderson
2024-10-10 0:37 ` Pierrick Bouvier
2024-10-09 15:08 ` [PATCH 21/23] accel/tcg: Remove CPUTLBDesc.fulltlb Richard Henderson
2024-10-10 0:38 ` Pierrick Bouvier [this message]
2024-10-09 15:08 ` [NOTYET PATCH 22/23] accel/tcg: Drop TCGCPUOps.tlb_fill Richard Henderson
2024-10-10 0:40 ` Pierrick Bouvier
2024-10-09 15:08 ` [NOTYET PATCH 23/23] accel/tcg: Unexport tlb_set_page* Richard Henderson
2024-10-09 16:27 ` [RFC PATCH 00/23] accel/tcg: Convert victim tlb to IntervalTree BALATON Zoltan
2024-10-09 17:10 ` Richard Henderson
2024-10-10 0:50 ` Pierrick Bouvier
2024-10-15 0:07 ` Richard Henderson
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